View ADT7518ARQ_78113.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY TECHNICAL DATA
a
SPI/I2C Compatible, Temperature Sensor, Four Channel ADC and Quad Voltage Output DAC
Preliminary Technical Data
FEATURES ADT7516 - Four 12-Bit DACs ADT7517 - Four 10-Bit DACs ADT7518 - Four 8-Bit DACs Buffered Voltage Output Guaranteed Monotonic By Design Over All Codes 10-Bit Temperature to Digital Converter 10-Bit Four Channel ADC : DC Input Bandwidth Input Range: 0 V to 2.25 V Temperature range: -40oC to +125oC Temperature Sensor Accuracy of 0.5oC Supply Range : + 2.7 V to + 5.5 V DAC Output Range: 0 - 2VREF Power-Down Current 1A Internal 2.25 VRef Option Double-Buffered Input Logic Buffered Reference Input Option Power-on Reset to Zero Volts Simultaneous Update of Outputs (LDAC Function) On-Chip Rail-to-Rail Output Buffer Amplifier I2C, SPITM, QSPITM, MICROWIRETM and DSP-Compatible 4wire Serial Interface 16-Lead QSOP Package
ADT7516/7517/7518
APPLICATIONS Portable Battery Powered Instruments Personal Computers Smart Battery Chargers Telecommunications Systems Electronic Test Equipment Domestic Appliances Process Control GENERAL DESCRIPTION
The ADT7516/7517/7518 combines a 10-Bit Temperature-to-Digital Converter, a 10-Bit Four Channel ADC and a quad 12/10/8-Bit DAC respectively, in a 16-Lead QSOP package. This includes a bandgap temperature sensor and a 10-bit ADC to monitor and digitize the temperature reading to a resolution of 0.25 oC. The ADT7516/17/18 operates from a single +2.7 V to + 5.5 V supply. The input voltage range on the ADC channels has a range of 0V to 2.25V and the input bandwidth is DC. The reference for the ADC channels is derived internally. The output voltage of the DAC ranges from 0 V to VDD , with an output voltage settling time of typ 7 msec. The ADT7516/17/18 provides two serial interface options, a four-wire serial interface which is compatible with SPITM, QSPITM, MICROWIRETM and DSP interface standards; and a two-wire SMBus/I2C interface. It features a standby mode that is controlled via the serial interface.
cont. next page
FUNCTIONAL BLOCK DIAGRAM
ADDRESS POINTER REGISTER
ON-CHIP TEMPERATURE SENSOR
D+/AIN1 D-/AIN2
INTERNAL TEMPERATURE VALUE REGISTER EXTERNAL TEMPERATURE VALUE REGISTER
DIGITAL MUX
THIGH LIMIT REGISTERS TLOW LIMIT REGISTERS VDD Limit REGISTERS AINHIGH LIMIT REGISTERS AINLOW LIMIT REGISTERS
CONTROL CONFIG. 1 REGISTER CONTROL CONFIG. 2 REGISTER CONTROL CONFIG. 3 REGISTER DAC CONFIGURATION REGISTERS LDAC CONFIGURATION REGISTERS
DAC A REGISTERS
STRING DAC A
2 VOUT-A
DIGITAL MUX
7
8
ANALOG MUX
LDAC/AIN3 AIN4
9 14
A-TO-D CONVERTER
VDD VALUE REGISTER
LIMIT COMPARATOR
DAC B REGISTERS
STRING DAC B
1
VOUT-B
DAC C REGISTERS
STRING DAC C
16 VOUT-C
VDD SENSOR
AIN1 VALUE REGISTER AIN2 VALUE REGISTER
AIN3 VALUE REGISTER AIN4 VALUE REGISTER
DAC D REGISTERS
STRING DAC D
15 VOUT-D
GAIN SELECT LOGIC
POWER DOWN LOGIC
ADT7516/17/18
STATUS REGISTERS
INTERRUPT MASK REGISTERS
10 INT/INT
INTERNAL REFERENCE
SMBus INTERFACE
6
VDD
5
GND
4
CS
13
SCL
12
SDA
11
ADD
9
LDAC/AIN3
3
VREF-IN
REV. PrH 01/'03
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
I 2 C is a registered trademark of Philips Corporation SPI and QSPI are trademarks of Motorola, INC. MICROWIRE is a trademark of National Semiconductor Corporation. The ADT7316/7317/7318 is protected by the following U.S. patent numbers and by other intellectual property rights : 6,169,442 6,097,239 US Patent Pending 5,867,012 5,764174 One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
cont. from P.1
The reference for the four DACs is derived either internally or from a reference pin. The outputs of all DACs may be updated simultaneously using the software LDAC function or external LDAC pin. The ADT7516/7517/ 7518 incorporates a power-on-reset circuit, which ensures
that the DAC output powers-up to zero volts and it remains there until a valid write takes place. The ADT7516/7517/7518's wide supply voltage range, low supply current and SPI/I2 C-compatible interface, make it ideal for a variety of applications, including personal computers, office equipment and domestic appliances.
ADT7516/ADT7517/ADT7518-SPECIFICATIONS1
(VDD=2.7 V to 5.5 V, GND=0 V, REFIN=2.25 V, unless otherwise noted) Parameter2
DAC DC PERFORMANCE3,4 ADT7518 Resolution Relative Accuracy Relative Accuracy Differential Nonlinearity ADT7517 Resolution Relative Accuracy Relative Accuracy Differential Nonlinearity ADT7516 Resolution Relative Accuracy Relative Accuracy Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Lower Deadband
Min
Typ
Max
Units
Conditions/Comments
8 0.15 tbd 0.02 10 0.5 tbd 0.05 12 2 tbd 0.02 0.4 0.3 20 tbd -12 -5 -60 200
1 tbd 0.25
Bits LSB LSB LSB Bits LSB LSB LSB Bits LSB LSB LSB % of FSR LSB % of FSR LSB mV mV
Excluding Offset and Gain errors Guaranteed Monotonic by design over all codes
4 tbd 0.5
Excluding Offset and Gain errors Guaranteed Monotonic by design over all codes
16 tbd 0.9 3 0.5 1.25 0.5 60 tbd
Excluding Offset and Gain errors Guaranteed Monotonic by design over all codes
Upper Deadband Offset Error Drift6 Gain Error Drift6 DC Power Supply Rejection Ratio6 DC Crosstalk 6 ADC DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match ADC Bandwidth ANALOG INPUTS Input Voltage Range AIN Conversion Time DC Leakage Current Input Capacitance Input Resistance 0 0
Lower Deadband exists only if Offset Error is Negative. See Figure 5. Upper Deadband exists if VREF = VDD and Offset plus Gain Error is positive. See Figure 6.
ppm of FSR/C ppm of FSR/C dB VDD = 10% V Reference Figure 4
10 2 0.9 2 0.5 2 0.5 DC 2.25 V DD 1 tbd
Bits LSB LSB % of FSR LSB % of FSR LSB Hz V V s s A pF
Max VDD = 5 V
712 44.5 tbd tbd
AIN1 to AIN4. C4 = 0 in Control Config. 3. AIN1 to AIN4. C4 = 1 in Control Config. 3. Averaging (16 samples) on. Averaging off.
-2-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
Parameter2
THERMAL CHARACTERISTICS
Min
Typ
Max
Units
Conditions/Comments
Internal Reference used. Averaging on.
INTERNAL TEMPERATURE SENSOR
Accuracy @ V DD=3.3V 10% 0.5 2 Accuracy @ VDD=5V 5% 2 3 Resolution Long Term Drift Conversion Time 0.5 25.92 1.62 0.5 2 3 1 3 4 10 C C C C C C Bits C/1000hrs ms ms TA = 40C TA = 0C to +85C TA = -40C to +125C TA = 40C TA = 0C to +85C TA = -40C to +125C Equivalent to 0.25C Averaging (16 samples) on. Averaging off.
EXTERNAL TEMPERATURE SENSOR
Accuracy @ V DD=3.3V 10% 1 2 3 1.5 3 C C C C C
Accuracy @ VDD=5V 5% 2
External Transistor = 2N3906. TA = 40C TA = 0C to +85C. TA = -40C to +125C TA = 40C TA = 0C to +85C
3 Resolution Conversion Time Output Source Current 16.8 1.05 180 11
4 10
C Bits ms ms A A
TA = -40C to +125C Equivalent to 0.25C Averaging (16 samples) on. Averaging off. High Level Low Level
THERMAL VOLTAGE OUTPUT
8-Bit DAC Output Resolution Scale Factor 10-Bit DAC Output Resolution Scale Factor
ROUND ROBIN UPDATE RATE6
1 8.79 17.58 0.25 2.2 4.39 29.48 1.842 44.86 2.8
C mV/C mV/C C mV/C mV/C ms ms ms ms
0-VREF Output. TA = -40C to +125C 0-2VREF Output. TA = -40C to +125C 0-VREF Output. TA = -40C to +125C 0-2VREF Output. TA = -40C to +125C Time to complete one measurement cycle. Pins 7 and 8 configured for AIN1 and AIN2 Pins 7 and 8 configured for AIN1 and AIN2 Pins 7 and 8 configured for D+ and DPins 7 and 8 configured for D+ and D-
Averaging Averaging Averaging Averaging
On Off On Off
DAC EXTERNAL REFERENCE INPUT 7 VREF Input Range VREF Input Impedance Reference Feedthrough Channel-to-Channel Isolation ON-CHIP REFERENCE Reference Voltage7 Temperature Coefficient 7 OUTPUT CHARACTERISTICS 7 Output Voltage 8 DC Output Impedance Short Circuit Current Power Up Time
1 >10 -90 -75 2.25 80 0.001 0.5 25 16 2.5 5
V DD
V M dB dB V ppm/ C
Buffered Reference Buffered reference and Power-Down Mode Frequency=10KHz Frequency=10KHz
V DD -0.001
V mA mA s s
This is a measure of the minimum and maximum drive capability of the output amplifier V DD = +5V V DD = +3V Coming out of Power Down Mode. VDD = +5 V Coming out of Power Down Mode. V DD = +3.3 V
REV. PrH
-3-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
DIGITAL INPUTS 7 Input Current VIL, Input Low Voltage VIH , Input High Voltage Pin Capacitance SCL, SDA Glitch Rejection LDAC Pulse Width DIGITAL OUTPUT Output High Voltage, VOH Output Low Voltage, V OL Output High Current, IOH 1 0.8 1.89 3 20 2.4 0.4 1 10 50 A V V pF ns ns V V mA V IN = 0V to V DD
All Digital Inputs Input Filtering Suppresses Noise Spikes of Less than 50ns. Edge triggered input. ISOURCE = ISINK = 200 A IOL = 3 mA V OH = 5 V
Output Capacitance, COUT
INT/INT Output Saturation Voltage
50 0.8 2.5 0 50 50 90 0 50 50 35 20 0 0 40 2.7 5.5 50 2 2.2 3 10 6.6 10
pF V s ns ns ns ns ns ns ns ns ns ns ns ns V ms mA mA A A W W
I OUT = 4 mA Fast-Mode I2C. See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2
I2 C
TIMING
CHARACTERISTICS 9,10
Serial Clock Period, t 1 Data In Setup Time to SCL High, t2 Data Out Stable after SCL Low, t3 SDA Low Setup Time to SCL Low (Start Condition), t4 SDA High Hold Time after SCL High (Stop Condition), t5 SDA and SCL Fall Time, t6
SPI TIMING CHARACTERISTICS 11, 12
CS to SCLK Setup Time, t 1 SCLK High Pulsewidth, t2 SCLK Low Pulse, t3 Data Access Time after SCLK Falling edge, t412 Data Setup Time Prior to SCLK Rising Edge, t5 Data Hold Time after SCLK Rising Edge, t6 CS to SCLK Hold Time, t7 CS to DOUT High Impedance, t8
POWER REQUIREMENTS VDD VDD Settling Time IDD (Normal Mode)14 IDD (Power Down Mode) Power Dissipation
TBD TBD TBD TBD
VDD settles to within 10% of it's final voltage level VDD = +3.3 V, VIH = VDD and VIL = GND VDD = +5 V, VIH = VDD and VIL = GND VDD = +3.3 V, VIH=VDD and VIL=GND VDD = +5 V, VIH=VDD and VIL=GND VDD = +3.3 V. Normal Mode VDD = +3.3 V. Shutdown Mode
Notes: 1 Temperature ranges are as follows: A Version: -40C to +125C. 2 See Terminology. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: ADT7516 (code 115 to 4095); ADT7517 (code 28 to 1023); ADT7518 (code 8 to 255) 5 See Terminology. 6 Round Robin is the continuous sequential measurement of the following channels : V DD, Internal Temperature, External Temperature/ (AIN1, AIN2), AIN3 and AIN4. 7 Guaranteed by Design and Characterization, not production tested 8 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage (V REF =V DD ) "Offset plus Gain" Error must be positive. 9 The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I 2C specification. Switching off the input filters improves the transfer rate but has a negative affect on the EMC behaviour of the part. 10 Guaranteed by design. Not tested in production. 11 Guaranteed by design and characterization, not production tested. 12 All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 13 Measured with the load circuit of Figure 3. 14 IDD spec. is valid for all DAC codes and fullscale analog input voltage. Interface inactive. All DACs and ADC active. Load currents excluded. Specifications subject to change without notice.
-4-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518 DAC AC CHARACTERISTICS1
Parameter2
Output Voltage Settling Time ADT7518 ADT7517 ADT7516 Slew Rate Major-Code Change Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion
(VDD = +2.7V to +5.5 V; RL=4k7 to GND; CL=200pF to GND; 4K7 to VDD; All specifications TMIN to TMAX unless otherwise noted.)
Max
8 9 10
Min Typ @ 25C
6 7 8 0.7 12 0.5 1 0.5 3 200 -70
Units
s s s V/s nV-s nV-s nV-s nV-s nV-s kHz dB
Conditions/Comments
V REF =V DD =+5V 1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex) 1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex) 1/4 Scale to 3/4 Scale change (400 Hex to C00 Hex) 1 LSB change around major carry.
V REF =2V0.1Vpp V REF =2.5V0.1Vpp. Frequency=10kHz.
NOTES 1 Guaranteed by Design and Characterization, not production tested 2 See Terminology Specifications subject to change without notice.
t1 SC L t4 SD A DA T A IN t3 SD A DA T A O U T t2 t5
t6
Figure 1. Diagram for I2C Bus Timing
CS
t1
SCLK
t2
t7
t3
DIN D7 D6 D5 D4 D3
t5
D2
t6
D1 D0 X X X X X X X
t8
X
t4
DOUT X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0
Figure 2. Diagram for SPI Bus Timing
200 A
I OL
VDD
47
TO OUTPUT PIN 1.6V CL 50pF
To DAC Ou tp ut 47 200pF
2 00 A
IO L
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
Figure 4. Load Circuit for DAC Outputs
REV. PrH
-5-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
ABSOLUTE MAXIMUM RATINGS1
Table 1. I2C Address Selection
VDD to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Reference Input voltage to GND Operating Temperature Range Storage Temperature Range Junction Temperature 16-Lead QSOP Package Power Dissipation2 Thermal Impedance3 JA Junction-to-Ambient JC Junction-to-Case IR Reflow Soldering Peak Temperature Time at Peak Temperature Ramp-up Rate Ramp-down Rate
Notes:
1
-0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3V -40C to +125C -65C to +150C +150C (Tj max - TA) / JA 105.44 C/W 38.8 C/W +220C (-0/+5C) 10 to 20 secs 2-3C/sec -6C/sec
ADD Pin Low Float High
I2C Address 1001 000 1001 010 1001 011
PIN CONFIGURATION QSOP
Vout -B
1
16 V out -C 15 Vout -D 14 AIN4
Vout -A 2 VrefIN CS GND VDD D+/AIN1 D-/AIN2 3 4 5 6 7 8
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Values relate to package being used on a 4-layer board. Junction-to-Case resistance is applicable to components featuring a preferential flow direction, eg. components mounted on a heat sink. Junction-to-Ambient resistance is more useful for air-cooled PCBmounted components.
ADT7516/ 7517/7518
TOP VIEW
(Not to Scale)
13 SCL/SCLK 12 SDA/DIN 11 DOUT/ADD 10 INT/INT 9 LDAC/AIN3
2 3
ORDERING GUIDE
Model ADT7518ARQ ADT7517ARQ ADT7516ARQ
Temperature Range -40C to +125C -40C to +125C -40C to +125C
DAC Resolution 8-Bits 10-Bits 12-Bits
Package Description 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP
Package Options RQ-16 RQ-16 RQ-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADT7516/7517/7518 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-6-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
ADT7516/7517/7518 PIN FUNCTION DESCRIPTION
Pin 1 2 3 4
Mnemonic V O U TB V OUT A V REF IN CS
Description Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Reference Input Pin for all four DACs.This input is buffered and has an input range from 1 V to VDD. SPI - Active low control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables the input register and data is transferred in on the rising edges and out on the falling edges of the subsequent serial clocks. It is recommended that this pin be tied high to VDD when operating the serial interface in I2C mode. Ground Reference Point for All Circuitry on the part. Analog and Digital Ground. Positive Supply Voltage, +2.7 V to +5.5 V. The supply should be decoupled to ground. D+. Positive connection to external temperature sensor. AIN1. Analog Input. Single ended analog input channel. Input range is 0 V to 2.25 V or 0 V to 5 V.
5 6 7
GND V DD D+/AIN1
8
D-/AIN2
D-. Negative connection to external temperature sensor. AIN2. Analog Input. Single ended analog input channel. Input range is 0 V to 2.25 V or 0 V to 5 V.
9
LDAC/ A I N 3
LDAC. Active low control input that transfers the contents of the input registers to their respective DAC registers. A falling edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum pulse width of 20ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows simultaneous update of all DAC outputs. Bit C3 of Control Configuration 3 register enables LDAC pin. Default is with LDAC pin controlling the loading of DAC registers. AIN3. Analog Input. Single ended analog input channel. Input range is 0 V to 2.25 V or 0 V to 5 V.
10 11
INT/INT DOUT/ADD
Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when temperature, VDD or AIN limits are exceeded. Default is active low. SPI Serial Data Output. Logic Output. Data is clocked out of any register at this pin. Data is clocked out on the falling edge of SCLK. Open Drain output - needs a pullup resistor. ADD - I2C serial bus address selection pin. Logic input. A low on this pin gives the address 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011. The I2C address set up by the ADD pin is not latched by the device until after this address has been sent twice. On the 8th SCL cycle of the second valid communication, the serial bus address is latched in. Any subsequent changes on this pin will have no affect on the I2C serial bus address.
12
SDA/DIN
SDA. I2C Serial Data Input. I2C serial data to be loaded into the parts registers is provided on this input. DIN. SPI Serial Data Input. Serial data to be loaded into the parts registers is provided on this input. Data is clocked into a register on the rising edge of SCLK.
13
SCL/SCLK
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of the ADT7516/7517/7518 and also to clock data into any register that can be written to. Analog input. Single ended analog input channel. Input range is 0 V to 2.25 V or 0 V to 5 V. Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
14 15 16
AIN4 V O U TD V O U TC
REV. PrH
-7-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
TERMINOLOGY RELATIVE ACCURACY
Relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus Code plots can be seen in TPCs 1, 2, and 3.
DIFFERENTIAL NONLINEARITY
is significantly accelerated due to the increase in rates of reaction within the semiconductor material. As a result of this operation, the lifetime of an integrated circuit is significantly accelerated due to the increase in rates of reaction within the semiconductor material.
DC POWER-SUPPLY REJECTION RATIO (PSRR)
Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. The DAC and ADC are guaranteed monotonic by design. Typical DAC DNL versus Code plots can be seen in TPCs 4, 5, and 6.
OFFSET ERROR
This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dBs. VREF is held at 2 V and VDD is varied 10%.
DC CROSSTALK
This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in V.
REFERENCE FEEDTHROUGH
This is a measure of the offset error of the DAC and the output amplifier. (See Figures 5 and 6.) It can be negative or positive. It is expressed in mV.
OFFSET ERROR MATCH
This is the difference in Offset Error between any two channels
GAIN ERROR
This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dBs.
CHANNEL-TO-CHANNEL ISOLATION
This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range.
GAIN ERROR MATCH
This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
This is the difference in Gain error between any two channels.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of fullscale range)/C.
GAIN ERROR DRIFT
Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).
DIGITAL FEEDTHROUGH
This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of fullscale range)/C.
LONG TERM TEMPERATURE DRIFT
Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device but is measured when the DAC is not being written to the. It is specified in nV secs and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s or vice versa.
DIGITAL CROSSTALK
This is a measure of the change in temperature error with the passage of time. It is expressed in C/1000hrs. The concept of long-term stability has been used for many years to describe by what amount an IC's parameter would shift during its lifetime. This is a concept that has been typically applied to both voltage references and monolithic temperature sensors. Unfortunately, integrated circuits cannot be evaluated at room temperature (25C) for 10 years or so to determine this shift. As a result, manufacturers very typically perform accelerated life-time testing of integrated circuits by operating ICs at elevated temperatures (between 125C and 150C) over a shorter period of time (typically, between 500 and 1000 hours). As a result of this operation, the lifetime of an integrated circuit
This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in stand-alone mode and is expressed in nV secs.
ANALOG CROSSTALK
This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a fullscale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV secs. -8- REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
DAC-TO-DAC CROSSTALK TOTAL HARMONIC DISTORTION
This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV secs.
MULTIPLYING BANDWIDTH
This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in dBs.
ROUND ROBIN
This term is used to describe the ADT7516/17/18 cycling through the available measurement channels in sequence, taking a measurement on each channel.
DAC OUTPUT SETTLING TIME
The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.
This is the time required, following a prescribed data change, for the output of a DAC to reach and remain within 0.5 LSB of the final value. A typical prescribed change is from 1/4 scale to 3/4 scale.
GAIN ERROR + OFFSET ERROR
OUTPUT VOL TAGE
NEGATIVE OFFSET ERROR
DAC CODE
ACTUA L IDEAL
L OWER DEADBAND CODES AMPL IFIER FOOTROOM
NEGATIVE OFFSET ERROR
Figure 5. DAC Transfer Function with Negative Offset
GAIN ERROR + OFFSET ERROR
UPPER DEADBAND CODES
OUTPUT VOL TAGE
ACTUAL IDEAL
POSITIVE OFFSET ERROR DAC C ODE
FULL SCALE
Figure 6. DAC Transfer Function with Positive Offset (VREF = VDD)
REV. PrH
-9-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
0 0 0
TITLE
TITLE
0
0
TITLE
0 0 TITLE 0 0
0
0
0
0
0
0 TITLE
0
0
0
0
0
0
0
0
0
0
0
0 TITLE
0
0
0
TPC 1. ADT7518 Typical DAC INL Plot
TPC 2. ADT7517 Typical DAC INL Plot
TPC 3. ADT7516 Typical DAC INL Plot
0
0
0
TITLE
0
0
TITLE
0 0 TITLE 0 0
TITLE
0
0
0
0
0
0 TITLE
0
0
0
0
0
0
0
0
0
0
0
0 TITLE
0
0
0
TPC 4. ADT7518 Typical DAC DNL Plot
TPC 5. ADT7517 Typical DAC DNL Plot
TPC 6. ADT7516 Typical DAC DNL Plot
0
0
0
TITLE
0
0
TITLE
0 0 TITLE 0 0
TITLE
0
0
0
0
0
0 TITLE
0
0
0
0
0
0
0
0
0
0
0
0 TITLE
0
0
0
TPC 7. ADT7518 DAC INL and DNL Error vs VREF
TPC 8. ADT7518 DAC INL Error and DNL TPC 9. ADT7518 DAC Offset Error and Error vs Temperature Gain Error vs Temperature
-10-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
0 0 0
TITLE
TITLE
0
0
TITLE
0 0 TITLE 0 0
0
0
0
0
0
0 TITLE
0
0
0
0
0
0
0
0
0
0
0
0 TITLE
0
0
0
TPC 10. DAC Offset Error and Gain Error vs VDD
TPC 11. DAC VOUT Source and Sink Current Capability
TPC 12. Supply Current vs. DAC Code
0
0
0
TITLE
0
0
TITLE
0 0 TITLE 0 0
TITLE
0
0
0
0
0
0 TITLE
0
0
0
0
0
0
0
0
0
0
0
0 TITLE
0
0
0
TPC 13. Supply Current vs. Supply Volt- TPC 14. Power-Down Current vs. Supply TPC 15. DAC Half-Scale Settling (1/4 to age Voltage 3/4 Scale Code Change)
0 0 0
TITLE
TITLE
0
0
TITLE
0 0 0
0
0
0
0
0
0 TITLE
0
0
0
0
0
0 TITLE
0
0
0
0
0
0
0 TITLE
0
0
0
TPC 16. Exiting Power-Down to MidscaleTPC 17. ADT7516 DAC Major-Code Transition Glitch Energy
TPC 18. DAC Multiplying Bandwidth (Small-Signal Frequency Response)
REV. PrH
-11-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
0 0
TITLE
0
TITLE
0 0 0
0
0
0
0 TITLE
0
0
0
0
0
0
0 TITLE
0
0
0
TPC 19. DAC Full-Scale Error vs. VREF
TPC 20. DAC-to-DAC Crosstalk
0
0
TITLE
0
TITLE
0 0 0 0 TITLE 0 0 0
0
0
0
0
0
0
0 TITLE
0
0
0
TPC 21. ADC DNL
TPC 22. ADC INL
0
0
TITLE
0
TITLE
0 0 0 0 TITLE 0 0 0
0
0
0
0
0
0
0 TITLE
0
0
0
TPC 23. PSRR vs Supply Ripple Frequency
TPC 24. Temperature Error @ 3.3 V and 5 V
-12-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
0 0
TITLE
0
TITLE
0 0 0
0
0
0
0 TITLE
0
0
0
0
0
0
0 TITLE
0
0
0
TPC 25. ADC Offset Error and Gain Error vs Temperature
TPC 26. ADC Offset Error and Gain Error vs VDD
REV. PrH
-13-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
ADT7516/17/18 OPERATION
Directly after the power-up calibration routine the ADT7516/17/18 goes into idle mode. In this mode the device is not performing any measurements and is fully powered up. All four DAC outputs are at 0V. To begin monitoring, write to Control Configuration 1 (address = 18h) register and set bit C0 = 1. The ADT7516/17/18 goes into it's power-up default measurement mode, which is Round Robin. The device proceeds to take measurements on the VDD channel, internal temperature sensor channel, external temperature sensor channel or AIN1 and AIN2, AIN3 and finally AIN4 . Once it finishes taking measurements on the AIN4 channel the device immediately loops back to start taking measurements on the VDD channel and repeats the same cycle as before. This loop continues until the monitoring is stopped by resetting bit C0 of Control Configuration 1 register to 0. It is also possible to continue monitoring as well as switching to Single channel mode by writing to Control Configuration 2 register (address = 19h) and setting bit C4 = 1. Further explanation of the Single channel and Round Robin measurement modes are given in later sections. All measurement channels have averaging enabled on them on power-up. Averaging forces the device to take an average of 16 readings before giving a final measured result. To disable averaging and consequently decrease the conversion time by a factor of 16, set C5 = 1 in Control Configuration 2 register. There are four single ended analog input channels on the ADT7516/17/18, AIN1 to AIN4. AIN1 and AIN2 are multiplexed with the external temperature sensors D+ and D- terminals. Bits C1 and C2 of Control Configuration 1 register (address = 18h) are used to select between AIN1/ 2 and external temperature sensor. The input range on the analog input channels is dependent on whether the ADC reference used is the internal VREF or VDD. To meet linearity specifications, it is recommended that the maximum VDD value is 5 V. Bit C4 of Control Configuration 3 register is used to select between the internal reference or VDD as the analog inputs ADC reference. Controlling the DAC outputs can be done by writing to the DACs MSB and LSB registers (addresses 10h - 17h). The power-up default setting is to have a low going pulse on the LDAC pin (pin 9) controlling the updating of the DAC outputs from the DAC registers. You can configure the updating of the DAC outputs to be controlled by methods other than the LDAC pin by setting C3 = 1 of the Control Configuration 3 register (address = 1Ah). The DAC Configuration register (address = 1Bh) and the LDAC Configuration register (address = 1Ch) can now be used to control the DAC updating. These two registers also control the output range of the DACs and selecting between the internal or external reference. DAC A and DAC B outputs can be configured to give a voltage output proportional to the temperature of the internal and external temperature sensors respectively. The dual serial interface defaults to the I2C protocol on power-up. To select and lock in the SPI protocol please follow the selection process as described in the Serial Interface Selection section. The I2C protocol cannot be
locked in, while the SPI protocol on selection is automatically locked in. The interface can only be switched back to be I2C when the device is powered off and on. When using I2C the CS pin should be tied to either VDD or GND. There are a number of different operating modes on the ADT7516/17/18 devices and all of them can be controlled by the configuration registers. These features consist of the INT/INT pin, enabling and disabling interrupts, polarity of the INT/INT pin, enabling and disabling the averaging on the measurement channels, SMBus timeout and software reset.
POWER-UP CALIBRATION
It is recommended that no communication to the part is initiated until approximately 5ms after VDD has settled to within 10% of it's final value. It is generally accepted that most systems take a maximum of 50ms to power-up. Power-up time is directly related to the amount of decoupling on the voltage supply line. During this 5ms after VDD has settled, the part is performing a calibration routine and any communication to the device will interrupt this routine and could cause erroneous temperature measurements. If it not possible to have VDD at it's nominal value by the time 50ms has elapsed or that communication to the device has started prior to VDD settling then it is recommended that a measurement be taken on the VDD channel before a temperature measurement is taken. The VDD measurement is used to calibrate out any temperature measurement error due to different supply voltage values.
FUNCTIONAL DESCRIPTION - VOLTAGE OUTPUT DAC
The ADT7516/7517/7518 has four resistor-string DACs fabricated on a CMOS process with resolutions of 12, 10 and 8 bits respectively. They contain four output buffer amplifiers and is written to via I2C serial interface or SPI serial interface. See Serial Interface Selection section for more information. The ADT7516/7517/7518 operates from a single supply of 2.7 V to 5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/s. All four DACs share a common reference input, namely VREFIN. The reference input is buffered to draw virtually no current from the reference source as it offers the source a high impedance input. The devices have a power-down mode, in which all DACs may be turned off completely with a high-impedance output. Each DAC output will not be updated until it receives the LDAC command. Therefore while the DAC registers would have been written to with a new value, this value will not be represented by a voltage output until the DACs have received the LDAC command. Reading back from any DAC register prior to issuing an LDAC command will result in the digital value that corresponds to the DAC output voltage. Thus the digital value written to the DAC register cannot be read back until after the LDAC command has been initiated. This LDAC command can
-14-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
be given by either pulling the LDAC pin low (falling edge loads DACs), setting up Bits D4 and D5 of DAC Configuration register (address = 1Bh) or using the LDAC register (address = 1Ch. When using the LDAC pin to control DAC register loading, the low going pulse width should be 20ns minimum. The LDAC pin has to go high and low again before the DAC registers can be reloaded.
Digital-to-Analog Section
R R R TO OUTPUT AMPLIFIER
The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREFIN pin or the on-chip reference of 2.25 V provides the reference voltage for the corresponding DAC. Figure 7 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by: VREF * D VOUT = ---------2N where D=decimal equivalent of the binary code which is loaded to the DAC register; 0-255 for ADT7518 (8-Bits) 0-1023 for ADT7517 (10-Bits) 0-4095 for ADT7516 (12-Bits) N = DAC resolution.
VREF-IN
R R
Figure 8. Resistor String
DAC Reference Inputs
There is an input reference pin for the DACs. This reference input is buffered.
VREF-IN
2.25 V Internal VREF
REFERENCE BUFFER GAIN MODE (GAIN=1 OR 2) Int VREF VOUTA
STRING DAC A STRING DAC B
INPUT REGISTER
DAC REGISTER
RESISTOR STRING
STRING DAC C STRING DAC D
OUTPUT BUFFER AMPLIFIER
Figure 7. Single DAC channel architecture
Resistor String
Figure 9. DAC Reference Buffer Circuit
The resistor string section is shown in Figure 8. It is simply a string of resistors, each of value 603 approximately. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
The advantage with the buffered input is the high impedance it presents to the voltage source driving it. The user can have an external reference voltage as low as 1 V and as high as VDD. The restriction of 1 V is due to the footroom of the reference buffer. The LDAC Configuration register controls the option to select between internal and external voltage references. The default setting is for external reference selected.
Output Amplifier
The output buffer amplifier is capable of generating output voltages to within 1mV of either rail. Its actual range depends on the value of VREF, GAIN and offset error. If a gain of 1 is selected (Bits 0-3 of DAC Configuration register = 0) the output range is 0.001 V to VREF. If a gain of 2 is selected (Bits 0-3 of DAC Configuration register = 1) the output range is 0.001 V to 2VREF. However because of clamping the maximum output is limited to VDD - 0.001V.
REV. PrH
-15-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
VDD I
OPTIONAL CAPACITOR, UP TO 3nF MAX. CAN BE ADDED TO IMPROVE HIGH FREQUENCY NOISE REJECTION IN NOISY ENVIRONMENTS
N xI
I BIAS
D+
C1
VOUT+ TO ADC V OUT-
REMOTE SENSING TRANSISTOR (2N3906)
DLOWPASS FILTER fc = 65kHz
BIAS DIODE
Figure 10. Signal Conditioning for External Diode Temperature Sensor
The output amplifier is capable of driving a load of 4k7 to GND or VDD, in parallel with 200pF to GND or VDD. See Figure 4. The source and sink capabilities of the output amplifier can be seen in the plot in TPC 11. The slew rate is 0.7V/s with a half-scale settling time to +/-0.5 LSB (at 8 bits) of 6s.
THERMAL VOLTAGE OUTPUT
The ADT7516/17/18 has the capability of outputting a voltage that is proportional to temperature. DAC A output can be configured to represent the temperature of the internal sensor while DAC B output can be configured to represent the external temperature sensor. Bits C5 and C6 of Control Configuration 3 register select the temperature proportional output voltage. Each time a temperature measurement is taken the DAC output is updated. The output resolution for the ADT7518 is 8 bits with 1C change corresponding to one LSB change. The output resolution for the ADT7516 and ADT7517 is capable of 10 bits with 0.25C change corresponding to one LSB change. The default output resolution for the ADT7516 and ADT7517 is 8 bits. To increase this to 10 bits, set C1 = 1 of Control Configuration 3 register. The default output range is 0V-VREF and this can be increased to 0V2VREF. Increasing the output voltage span to 2VREF can be done by setting D0 = 1 for DAC A (Internal Temperature Sensor) and D1 = 1 for DAC B (External Temperature Sensor) in DAC Configuration register (address 1Bh). The output voltage is capable of tracking a max temperature range of -128C to +127C but the default setting is 40C to +127C. If the output voltage range is 0V-VREF (VREF = 2.25 V) then this corresponds to 0V representing -40C and 1.48V representing +127C. This of course will give an upper deadband between 1.48V and VREF. The Internal and External Analog Temperature Offset registers can be used to vary this upper deadband and consequently the temperature that 0V corresponds to. Tables 2 and 3 give examples of how this is done using a DAC
output voltage span of VREF and 2VREF respectively. Simply write in the temperature value, in 2's complement format, that you want 0V to start at. For example, if you are using the DAC A output and you want 0V to start at 40C then program D8h into the Internal Analog Temperature Offset register (address 21h). This is an 8-bit register and thus only has a temperature offset resolution of 1C for all device models. Use the following formulas to determine the value to program into the offset registers. Negative temperatures : Offset Register Code(d)* = (0V Temp) + 128
*D7 of Offset Register Code is set to 1 for negative temperatures.
Example :
Offset Register Code(d) = (-40) + 128 = 88d = 58h
Since a negative temperature has been inputted into the equation, DB7 (MSB) of the Offset Register code is set to a 1. Therefore 58h becomes D8h.
58h + DB7(1) D8h
Positive temperatures : Offset Register Code(d) = 0V Temp
Example :
Offset Register Code (d) = 10d = 0Ah Table 2. Thermal Voltage Output (0V-VREF)
O/P Voltage 0V 0.5V 1V 1.12V
Default C -40 +17 +73 +87
Max C -128 -71 -15 -1
Sample C 0 +56 +113 +127
-16-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
VDD
I
N xI
I BIAS
VOUT+ TO ADC V OUTINTERNAL SENSE TRANSISTOR
BIAS DIODE
Figure 11. Top Level Structure of Internal Temperature Sensor
1.47V 1.5V 2V 2.25V
+127 UDB* UDB* UDB*
+39 +42 +99 +127
UDB* UDB* UDB* UDB*
4.5V
UDB*
+127
UDB*
* Upper deadband has been reached. DAC output is not capable of increasing. Reference Figure 6.
* Upper deadband has been reached. DAC output is not capable of increasing. Reference Figure 6.
The following equation is used to work out the various temperatures for the corresponding 8-bit DAC output :8-Bit Temp = (DAC O/P / 1 LSB) + ( 0V Temp)
Table 3.
Thermal Voltage Output, (0V-2VREF)
O/P Voltage 0V 0.25V 0.5V 0.75V 1V 1.12V 1.47V 1.5V 2V 2.25V 2.5V 2.75V 3V 3.25V 3.5V 3.75V 4V 4.25V REV. PrH
Default C -40 -26 +12 +3 +17 +23 +43 +45 +73 +88 +102 +116 UDB* UDB* UDB* UDB* UDB* UDB*
Max C -128 -114 -100 -85 -71 -65 -45 -43 -15 0 +14 +28 +42 +56 +70 +85 +99 +113
Sample C 0 14 +28 43 +57 +63 +83 +85 +113 +127 UDB* UDB* UDB* UDB* UDB* UDB* UDB* UDB*
For example, if the output is 1.5V, VREF = 2.25 V, 8-bit DAC has an LSB size = 2.25V/256 = 8.79x10-3, and 0V Temp is at -128C then the resultant temperature works out to be :(1.5 / 8.79x10-3) + (-128) = +43C
The following equation is used to work out the various temperatures for the corresponding 10-bit DAC output :10-Bit Temp = ((DAC O/P / 1 LSB)x0.25) + ( 0V Temp)
For example, if the output is 0.4991V, VREF = 2.25 V, 10bit DAC has an LSB size = 2.25V/1024 = 2.197x10-3, and 0V Temp is at -40C then the resultant temperature works out to be :((0.4991 /2.197x10-3)x0.25) + (-40) = +16.75C
Figure 12 shows a graph of DAC output vs temperature for a VREF = 2.25 V.
-17-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
2.25 2.10 1.95 D A C O U T P U T (V ) 1.80 1.65 1.50 1.35 1.20 1.05 0.90 0.75 0.60 0.45 0 V = 0'C 0.30 0.15 0.00 10 0 V = -128'C 0 V = -40'C
AIN1
AIN2
AIN3
AIN4
M U L T I P L E X E R
10-Bi t Resi stor-Strin g ADC
Figure 13. Quad Analog Input Path
CONVERTER OPERATION
20 30 40 50 60 70 80 90 100 110 120 127
-128 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
Temperature ('C)
Figure 12. DAC Output vs Temperature, VREF = 2.25 V
The analog input channels use a successive approximation ADC based around a resistor-string DAC. Figures 14 and 15 show simplified schematics of the ADC. Figure 14 shows the ADC during acquisition phase. SW2 is closed and SW1 is in position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on AIN.
FUNCTIONAL DESCRIPTION - ANALOG INPUTS
SINGLE-ENDED INPUTS
In t V R E F V DD
The ADT7516/17/18 offers four single-ended analog input channels. The analog input range is between 0 V to 2.25 V or 0 V to VDD. To maintain the linearity specification it is recommendated that the maximum VDD value be set at 5 V. Selection between the two input ranges is done by Bit C4 of Control Congifuration 3 Register (Address = 1Ah). Setting this bit to 0 sets up the analog input ADC reference to be sourced from the internal voltage reference of 2.25 V. Setting the bit to 1 sets up the ADC reference to be sourced from VDD. The ADC resolution is 10 bits and is mostly suitable for DC input signals. Bits C1:2 of Control Configuration 1 register (Address = 18h) are used to set up pins 7 and 8 as AIN1 and AIN2. Figure 13 shows the overall view of the four channel analog input path.
R ef
S A M P L IN G CA PA C ITO R
B
A
A IN
SW 1
R ES IST O R -S T R IN G DA C
A C Q U IS IT IO N PH A S E S W2
CO NTRO L LO G IC
C O M PA R AT OR R ef / 2
Figure 14. ADC Acquisition Phase
When the ADC eventually goes into conversion phase, see Figure 15, SW2 opens and SW1 moves to position B causing the comparator to become unbalanced. The control logic and the DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced the conversion is complete. The control logic generates the ADC output code. Figure 16 shows the ADC transfer function for the analog inputs.
-18-
REV. PrH
To ADC Val ue Regi ster
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
In t V R E F V DD R ef
SA M PL IN G CA PAC I TO R
B
A
A IN
SW 1
R ES IST OR -S T R IN G DAC
must be taken that the analog input signal never drops below the GND rail by more than 200mV. If this happens then the diode will become forward biased and start conducting current into the substrate. The 4pF capacitor is the typical pin capacitance and the resistor is a lumped component made up of the on-resistance of the multiplexer switch.
C O N VE R SI ON P H A SE SW 2
AIN
100 R
CO NT RO L LO G IC
C O M PA R ATO R Re f / 2
4 pF
Figure 17. Equivalent Analog Input ESD Circuit
Figure 15. ADC Conversion Phase
ADC TRANSFER FUNCTION
AIN INTERRUPTS
The output coding of the ADT7516/17/18 analog inputs is straight binary. The designed code transitions occur midway between successive integer LSB values (i.e. 1/ 2LSB, 3/2LSB, etc.). The LSB is VDD/1024 or Int VREF/ 1024, Int VREF = 2.25 V. The ideal transfer characteristic is shown in figure 16 below.
111...111 111...110
ADC CODE
111...000 011...111
1LSB = Int V REF/1024 1LSB = V DD/1024
The measured results from the AIN inputs are compared with the AIN VHIGH (greater than comparsion) and VLOW ( less than and equal to comparsion) limits. An interrupt occurs if the AIN inputs exceed or equal the limit registers. These voltage limits are stored in on-chip registers. Please note that the limit registers are 8 bits long while the AIN conversion result is 10 bits long. If the voltage limits are not masked out then any out of limit comparisons generate flags that are stored in Interrupt Status 1 Register (address = 00h) and one or more out-of limit results will cause the INT/INT output to pull either high or low depending on the output polarity setting. It is good design practice to mask out interrupts for channels that are of no concern to the application. Figure 18 showes the interrupt structure for the ADT7516/17/18. It gives a block diagram representation of how the various measurement channels affect the INT/ INT pin. FUNCTIONAL DESCRIPTION - MEASUREMENT
TEMPERATURE SENSOR
000...010 000...001 000...000
0V 1/2LSB +V REF -1LSB ANALOG INPUT
Figure 16. Single-Ended Transfer Function
To work out the voltage on any analog input channel, the following method can be used: 1 LSB = Reference (v) / 1024 Convert value read back from AIN Value register into decimal.
AIN Voltage = AIN Value (d) x LSB size
d = decimal Example: Internal Reference used. Therefore Vref = 2.25 V. AIN Value = 512d 1 LSB size = 2.25 V / 1024 = 2.197x10-3
AIN Voltage = 512 x 2.197x10-3 = 1.125 V ANALOG INPUT ESD PROTECTION
The ADT7516/7517/7518 contains an A-D converter with special input signal conditioning to enable operation with external and on-chip diode temperature sensors. When the ADT7516/7517/7518 is operating in single channel mode, the A to D converter continually processes the measurement taken on one channel only. This channel is preselected by bits C0:C2 in Control Configuration 2 Register (address 19h). When in Round Robin mode the analog input multiplexer sequentially selects the VDD input channel, the on-chip temperature sensor to measure its internal temperature, either the external temperature sensor or AIN1 and AIN2, AIN3 and then AIN4. These signals are digitized by the ADC and the results stored in the various Value Registers. The measured results from the temperature sensors are compared with the Internal and External, THIGH, TLOW limits. These temperature limits are stored in on-chip registers. If the temperature limits are not masked out then any out of limit comparisons generate flags that are stored in Interrupt Status 1 Register. One or more out-of
Figure 17 shows the input structure on any on the analog input pins that provides ESD protection. The diode provides the main ESD protection for the analog inputs. Care
REV. PrH
-19-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
S/W Reset
INTERRUPT STATUS REGISTER 1 (TEMP AND AIN1 to AIN4)
Internal Temp
STATUS BITS
External Temp
VDD INTERRUPT MASK REGISTERS INT/INT (Latched Output) Diode Fault
WATCHDOG LIMIT COMPARISONS
INTERRUPT STATUS REGISTER 2 (VDD)
STATUS BIT
AIN1-AIN4
Read Reset
CONTROL CONFIGURATION REGISTER 1
INT/INT ENABLE BIT
Figure 18. ADT7516/17/18 Interrupt Structure
limit results will cause the INT/INT output to pull either high or low depending on the output polarity setting. Theoretically, the temperature sensor and ADC can measure temperatures from -128oC to +127oC with a resolution of 0.25oC. However, temperatures outside TA are outside the guaranteed operating temperature range of the device. Temperature measurement from -128oC to +127oC is possible using an external sensor. Temperature measurement is initiated by three methods. The first method is applicable when the part is in single channel measurement mode. The temperature is measured 16 times and internally averaged to reduce noise. The total time to measure a temperature channel is typically 25.92ms (1.62ms x 16) for the internal temperature sensor and 16.8ms (1.05ms x 16) for the external temperature sensor. The new temperature value is loaded into the Temperature Value Register and ready for reading by the I2C or SPI interface. The user has the option of disabling the averaging by setting a bit (Bit 5) in the Control Configuration Register 2 (address 19h). The ADT7516/7517/ 7518 defaults on power-up with the averaging enabled. The second method is applicable when the part is in Round Robin measurement mode. The part measures both the internal and external temperature sensors as it cycles through all possible measurement channels. The two temperature channels are measured each time the part runs a round robin sequence. In round robin mode the part is continuously measuring all channels. Temperature measurement is also initiated after every read or write to the part when the part is in either single channel measurement mode or Round Robin measurement mode. Once serial communication has started, any conversion in progress is stopped and the ADC reset. Conversion
will start again immediately after the serial communication has finished. The temperature measurement proceeds normally as described above.
V DD MONITORING
The ADT7516/17/18 also has the capability of monitoring it's own power supply. The part measures the voltage on it's VDD pin to a resolution of 10 bits. The resultant value is stored in two 8-bit registers, the two LSBs stored in register address 03h and the eight MSBs are stored in register address 06h. This allows the user to have the option of just doing a one byte read if 10-bit resolution is not important. The measured result is compared with VHIGH and VLOW limits. If the VDD interrupt is not masked out then any out-of-limit comparison generates a flag in Interrupt Status 2 Register and one or more out-of-limit results will cause the INT/INT output to pull either high or low depending on the output polarity setting. Measuring the voltage on the VDD pin is regarded as monitoring a channel along with the Internal, External and AIN channels. You can select the VDD channel for single channel measurement by setting Bit C4 = 1 and setting Bit C0 to Bit C2 to all 0's in Control Configuration 2 register. When measuring the VDD value the reference for the ADC is sourced from the Internal Reference. Table 4 shows the data format. As the max VCC voltage measurable is 7 V, internal scaling is performed on the VCC voltage to match the 2.25V internal reference value. Below is an example of how the transfer function works. VDD = 5 V ADC Reference = 2.25 V 1 LSB = ADC Reference / 2^10 REV. PrH
-20-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
= 2.25 / 1024 = 2.197mV Scale Factor = Fullscale VCC / ADC Reference = 7 / 2.25 = 3.11 Conversion Result = VDD / ((7/Scale Factor) x LSB size) = 5 / (3.11 x 2.197mV) = 2DBh
TABLE 4. VDD Data Format, VREF = 2.25 V
Round Robin. Setting Bit 4 of Control Configuration 2 (address 19h) disables the Round Robin mode and in turn sets up the single channel mode. The single channel mode is where only one channel, eg. Internal temperature sensor, is measured in each conversion cycle. The time taken to monitor all channels will normally not be of interest, as the most recently measured value can be read at any time. For applications where the Round Robin time is important, it can be easily calculated. As mentioned previously a conversion on the internal temperature channel takes 25.92 ms, on the external temperature channel it takes 16.8ms, on the VDD and AIN channels it takes 712 us. These values are typical times and the channels have averaging on. This means that each channel is measured 16 times and internally averaged to reduce noise. The total cycle time for VDD, AIN1 to AIN4 and internal temperature is therefore nominally :
712s + (4 x 712s) + 25.92ms = 29.48 ms
VDD Value
Digital Output Binary Hex 16E 1B7 200 249 292 2DB 324 36D 3B6 3FF
2.5 V 3V 3.5 V 4V 4.5 V 5V 5.5 V 6V 6.5 V 7V
ON-CHIP REFERENCE
01 0110 1110 01 1011 0111 10 0000 0000 10 0100 1001 10 1001 0010 10 1101 1011 11 0010 0100 11 0110 1101 11 1011 0110 11 1111 1111
The total cycle time with averaging off is:
29.48 ms / 16 = 1.842 ms
The total cycle time for VDD, AIN3, AIN4, internal temperature and external temperature is therefore nominally :
712s + (2 x 712s) + 25.92ms + 16.8ms = 44.86 ms
The total cycle time with averaging off is:
44.86 ms / 16 = 2.8 ms SINGLE CHANNEL MEASUREMENT
The ADT7516/17/18 has an on-chip 1.2 V band-gap reference which is gained up by a switched capacitor amplifier to give an output of 2.25 V. The amplifier is powered up for the duration of the device monitoring phase and is powered down once monitoring is disabled. This saves on current consumption. On power-up the default mode is to have the internal reference selected as the reference for the ADC. The ADC is used for measuring VDD, internal temperature sensor, external temperature sensor and AIN inputs. The internal reference is always used when measuring VDD, the internal and external temperature sensors. The external reference is the default power-up reference for the DACs.
ROUND ROBIN MEASUREMENT
Setting C4 of Control Configuration 2 register enables the single channel mode and allows the ADT7516/17/18 to focus on one channel only. A channel is selected by writing to Bits C0:C2 in register Control Configuration 2 register. For example, to select the VDD channel for monitoring write to the Control Configuration 2 register and set C4 to 1 (if not done so already), then write all 0's to bits C0 to C2 . All subsequent conversions will be done on the VDD channel only. To change the channel selection to the Internal temperature channel, write to the Control Configuration 2 register and set C0 = 1. When measuring in single channel mode, conversions on the channel selected occur directly after each other. Any communication to the ADT7516/17/18 stops the conversions but they are restarted once the read or write operation is completed.
MEASUREMENT METHOD
On power-up the ADT7516/17/18 goes into Round Robin mode but monitoring is disabled. Setting Bit C0 of Configuration Register 1 to a 1 enables conversions. It sequences through all the available channels taking a measurement from each in the following order of VDD , Internal temperature sensor, External temperature sensor/ (AIN1 and AIN2), AIN3 and AIN4. Pin 7 and pin 8 can be configured to be either external temperature sensor pins or stand alone analog input pins. Once conversion is completed on the AIN4 channel, the device loop around for another measurement cycle. This method of taking a measurement on all the channels in one cycle is called REV. PrH
INTERNAL TEMPERATURE MEASUREMENT The ADT7516/7517/7518 contains an on-chip bandgap temperature sensor, whose output is digitized by the onchip ADC. The temperature data is stored in the Internal Temperature Value Register. As both positive and negative temperatures can be measured, the temperature data is stored in two's complement format, as shown in Table 5. The thermal characteristics of the measurement sensor could change and therefore an offset is added to the measured value to enable the transfer function to match the -21-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
thermal characteristics. This offset is added before the temperature data is stored. The offset value used is stored in the Internal Temperature Offset Register. EXTERNAL TEMPERATURE MEASUREMENT The ADT7516/7517/7518 can measure the temperature of one external diode sensor or diode-connected transistor. The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about -2mV/oC. Unfortunately, the absolute value of Vbe, varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass-production. The time taken to measure the external temperature can be reduced by setting C0 of Control Config. 3 register (1Ah). This increases the ADC clock speed from 1.4KHz to 22KHz but the analog filters on the D+ and D- input pins are switched off to accommodate the higher clock speeds. Running at the slower ADC speed, the time taken to measure the external temperature is 16.8ms while on the fast ADC this time is reduced to 712s. The technique used in the ADT7516/7517/7518 is to measure the change in Vbe when the device is operated at two different currents. This is given by: Vbe = KT/q x ln(N) where: K is Boltzmann's constant q is charge on the carrier T is absolute temperature in Kelvins N is ratio of the two currents Figure 10 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor. If a discrete transistor is used, the collector will not be grounded, and should be linked to the base. If a PNP transistor is used the base is connected to the D- input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D- input and the base to the D+ input. We recommend that a 2N3906 be used as the external transistor. To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D- input. As the sensor is operating in a noisy environment, C1 is provided as a noise filter. See the section on layout considerations for more information on C1. To measure Vbe, the sensor is switched between operating currents of I and N x I. The resulting waveform is passed through a lowpass filter to remove noise, thence to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce
Figure 19. Arrangement of Signal Tracks
GND D-
a DC voltage proportional to Vbe. This voltage is measured by the ADC to give a temperature output in 10-bit two's complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles.
LAYOUT CONSIDERATIONS
Digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. The following precautions should be taken: 1. Place the ADT7516/17/18 as close as possible remote sensing diode. Provided that the worst sources such as clock generators, data/address CRTs are avoided, this distance can be 4 to 8 to the noise buses and inches.
2. Route the D+ and D- tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. 3. Use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended.
GND 10 mil. 10 mil. D+ 10 mil. 10 mil. 10 mil. 10 mil. 10 mil.
4. Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/ solder joints are used, make sure that they are in both the D+ and D- path and at the same temperature. Thermocouple effects should not be a major problem as 1oC corresponds to about 240V, and thermocouple voltages are about 3V/oC of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200mV. 5. Place 0.1F bypass and 2200pF input filter capacitors close to the ADT7516/17/18. 6. If the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. This will work up to about 6 to 12 feet. 7. For really long distances (up to 100 feet) use shielded twisted pair such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D- and the shield to GND close to the ADT7516/17/18. Leave the remote end of the shield unconnected to avoid ground loops. Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect
-22-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
the measurement. When using long cables, the filter capacitor may be reduced or removed. Cable resistance can also introduce errors. 1 tance introduces about 0.5oC error. series resisbits long. If the limits are not masked out then any out-oflimit comparisons generate flags that are stored in Interrupt Status 1 Register (address = 00h) and Interrupt Status 2 Register (address = 01h). One or more out-of limit results will cause the INT/INT output to pull either high or low depending on the output polarity setting. It is good design practice to mask out interrupts for channels that are of no concern to the application. Figure 18 shows the interrupt structure for the ADT7516/ 17/18. It gives a block diagram representation of how the various measurement channels affect the INT/INT pin.
ADT7516/7517/7518 REGISTERS
TEMPERATURE VALUE FORMAT
One LSB of the ADC corresponds to 0.25C. The ADC can theoretically measure a temperature span of 255 C. The internal temperature sensor is guaranteed to a low value limit of -40 C. It is possible to measure the full temperature span using the external temperature sensor. The temperature data format is shown in Tables 5. The result of the internal or external temperature measurements is stored in the temperature value registers, and is compared with limits programmed into the Internal or External High and Low Registers. TABLE 5. Temperature Data Format (Internal and External Temperature) Temperature -40 C -25 C -10 C -0.25 C 0 C +0.25 C +10 C +25 C +50 C +75 C +100 C +105 C +125 C Digital Output 11 0110 0000 11 1001 1100 11 1101 1000 11 1111 1111 00 0000 0000 00 0000 0001 00 0010 1000 00 0110 0100 00 1100 1000 01 0010 1100 01 1001 0000 01 1010 0100 01 1111 0100
The ADT7516/17/18 contains registers that are used to store the results of external and internal temperature measurements, VDD value measurements, analog input measurements, high and low temperature limits, supply voltage and analog input limits, set output DAC voltage levels, configure multipurpose pins and generally control the device. A description of these registers follows. The register map is divided into registers of 8-bits long. Each register has it's own indvidual address but some consist of data that is linked with other registers. These registers hold the 10-bit conversion results of measurements taken on the Temperature, VDD and AIN channels. For example, the 8 MSBs of the VDD measurement are stored in register address 06h while the 2 LSBs are stored in register address 03h. The link involved between these types of registers is that when the LSB register is read first then the MSB registers associated with that LSB register are locked to prevent any updates. To unlock these MSB registers the user has only to read any one of them, which will have the affect of unlocking all previously locked MSB registers. So for the example given above if register 03h was read first then MSB registers 06h and 07h would be locked to prevent any updates to them. If register 06h was read then this register and register 07h would be subsequently unlocked.
1st READ COMMAND
LSB REGISTER
OUTPUT DATA
LOCK ASSOCIATED MSB REGISTERS
Figure 20. Phase 1 of 10-Bit Read
Temperature Conversion Formula: 1. Positive Temperature = ADC Code/4 2. Negative Temperature = (ADC Code* - 512)/4
*DB9 is removed from the ADC Code
UNLOCK ASSOCIATED MSB REGISTERS
2nd READ COMMAND
MSB REGISTER
OUTPUT DATA
Figure 21. Phase 2 of 10-Bit Read
INTERRUPTS
The measured results from the internal temperature sensor, external temperature sensor, VDD pin and the AIN inputs are compared with the THIGH/VHIGH (greater than comparison) and TLOW/VLOW (greater than or equal to comparison) limits. An interrupt occurs if the measurement exceeds or equals the limit registers. These limits are stored in on-chip registers. Please note that the limit registers are 8 bits long while the conversion results are 10 REV. PrH
If an MSB register is read first, it's corresponding LSB register is not locked thus leaving the user with the option of just reading back 8 bits (MSB) of a 10-bit conversion result. Reading an MSB register first does not lock up other MSB registers and likewise reading an LSB register first does not lock up other LSB registers.
Table 6. List of ADT7516/7517/7518 Registers
-23-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
RD/WR Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh Interrupt Status 1 Interrupt Status 2 RESERVED Internal Temp & VDD LSBs External Temp & AIN 1-4 LSBs RESERVED VDD MSBs Internal Temperature MSBs External Temp MSBs/ AIN 1 MSBs AIN 2 MSBs AIN 3 MSBs AIN 4 MSBs 00h 00h 00h 00h 00h 00h 31h-4Ch 00h 00h 00h 4Dh 4Eh 4Fh 0Ch-0Fh RESERVED 00h 50h-7Eh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h DAC A LSBs (ADT7516/17 only) DAC A MSBs DAC B LSBs (ADT7516/17 only) DAC B MSBs DAC C LSBs (ADT7516/17 only) DAC C MSBs DAC D LSBs (ADT7516/17 only) DAC D MSBs Control CONFIG 1 Control CONFIG 2 Control CONFIG 3 DAC CONFIG LDAC CONFIG Interrupt Mask 1 Interrput Mask 2 Internal Temp Offset External Temp Offset Internal Analog Temp Offset External Analog Temp Offset VDD V HIGH Limit VDD VLOW Limit Internal T HIGH Limit Internal TLOW Limit 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h D8h D8h C7h 62h 64h C9h D2 D1 Bit D0 Function 1 when Internal Temp Value exceeds THIGH limit. Any internal temperature reading greater than the limit set will cause an out of limit event. 1 when Internal Temp Value exceeds TLOW limit. Any internal temperature reading less than or equal to the limit set will cause an out of limit event. This status bit is linked to the configuration of pins 7 and 8. If configured for External Temperature Sensor REV. PrH D7 0*
Interrupt Status 1 Register (Read only) [Add. = 00h]
Name
Power-on Default
27h 28h
External THIGH / AIN1 VHIGH Limits External TLOW / AIN1 VLOW Limits RESERVED AIN 2 VHIGH Limit AIN 2 VLOW Limit AIN 3 VHIGH Limit AIN 3 VLOW Limit AIN 4 VHIGH Limit AIN 4 VLOW Limit RESERVED
FFh 00h
00h 00h 29h-2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h
FFh 00h FFh 00h FFh 00h
Device ID Manufacturer's ID Silicon Revision
03h/0Bh/07h 41h 00h
RESERVED
00h
7F
SPI Lock Status
00h
80-FFh
RESERVED
00h
This 8-bit read only register reflects the status of some of the interrupts that can cause the INT/INT pin to go active. This register is reset by a read operation provided that any out of limit event has been corrected. It is also reset by a software reset.
Table 7. Interrupt Status 1 Register
D6 0*
D5 0*
D4 0*
D3 0*
D2 0*
D1 0*
D0 0*
*Default settings at Power-up.
-24-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
then this bit is 1 when External Temp Value exceeds THIGH limit. The default value for this limit register is -1oC so any external temperature reading greater than the limit set will cause an out of limit event. If configured for AIN1 and AIN2 then this bit is 1 when AIN1 Input Voltage exceeds VHIGH or VLOW limits. D3 1 when External Temp Value exceeds TLOW limit. The default value for this limit register is 0oC so any external temperature reading less than or equal to the limit set will cause an out of limit event. 1 indicates a fault (open or short) for the external temperature sensor. 1 when AIN2 voltage is greater than corresponding VHIGH limit. 1 when AIN2 voltage is less than or equal to corresponding VLOW limit. 1 when AIN3 voltage is greater than corresponding VHIGH limit. 1 when AIN3 voltage is less than or equal to corresponding VLOW limit. 1 when AIN4 voltage is greater than corresponding VHIGH limit. 1 when AIN4 voltage is less than or equal to corresponding VLOW limit.
Table 9. Internal Temp/VDD LSBs
D7 N/A N/A
D6 N/A N/A
D5 N/A N/A
D4 N/A N/A
D3 V1 0*
D2 LSB 0*
D1 T1 0*
D0 LSB 0*
*Default settings at Power-up.
Bit D0 D1 D2 D3
Function LSB of Internal Temperature Value B1 of Internal Temperature Value LSB of V DD Value B1 of VDD Value
D4 D5
D6
EXTERNAL TEMPERATURE VALUE and ANALOG INPUTS 1-4 REGISTER LSBS (Read only) [Add. = 04h]
D7
This is a 8-bit read-only register. Bits D2 - D7 store the two LSBs of the analog inputs AIN2 - AIN4. Bits D0 and D1 are used to store the two LSBs of either the External Temperature Value or AIN1 input value. The type of input for D0 and D1 is selected by Bits C1:C2 of Control Configuration 1.
Table 10. External Temperature & AIN 1-4 LSBs
D7
Interrupt Status 2 Register (Read only) [Add. = 01h]
D6
A4LSB
D5
A3
D4
A3LSB
D3
A2
D2
A2LSB
D1
T/A
D0
T/ALSB
This 8-bit read only register reflects the status of the VDD interrupt that can cause the INT/INT pin to go active. This register is reset by a read operation provided that any out of limit event has been corrected. It is also reset by a software reset.
Table 8. Interrupt Status 2 Register
A4
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at Power-up.
Bit D0 D1 N/A D0 N/A D1 D2 Bit D4 Function 1 when VDD value is greater than corresponding VHIGH limit. 1 when VDD is less than or equal to corresponding VLOW limit. D3 D4 D5 D6 D7
Function LSB of External Temperature Value or AIN 1 Value Bit 1 of External Temperature Value or AIN 1 Value LSB of AIN 2 Value Bit 1 of AIN 2 Value LSB of AIN 3 Value Bit 1 of AIN 3 Value LSB of AIN 4 Value Bit 1 of AIN 4 Value
D7 N/A
D6 N/A
D5 N/A
D4 0*
D3 N/A
D2 N/A
*Default settings at Power-up.
INTERNAL TEMPERATURE VALUE/VDD VALUE REGISTER LSBs (Read only) [Add. = 03h]
VDD VALUE REGISTER MSBS (Read only) [Add. = 06h]
This Internal Temperature Value and VDD Value Register is a 8-bit read-only register. It stores the two LSBs of the 10-bit temperature reading from the internal temperature sensor and also the two LSBs of the 10-bit supply voltage reading.
This 8-bit read only register stores the supply voltage value. The 8 MSBs of the 10-bit value are stored in this register.
Table 11. VDD Value MSBs
D7
D6
D5
D4
D3
D2
D1
D0
REV. PrH
-25-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
V9 0* V8 0* V7 0* V6 0* V5 0* V4 0* V3 0* V2 0* to give the full 10-bit conversion result of the analog value on the AIN 3 pin.
Table 15. AIN 3 MSBs
*Default settings at Power-up.
D7
INTERNAL TEMPERATURE VALUE REGISTER MSBS (Read only) [Add. = 07h]
D6 A8 0*
D5 A7 0*
D4 A6 0*
D3 A5 0*
D2 A4 0*
D1 A3 0*
D0 A2 0*
MSB 0*
This 8-bit read only register stores the Internal Temperature value from the internal temperature sensor in twos complement format. The 8 MSBs of the 10-bit value are stored in this register.
Table 12. Internal Temperature Value MSBs
*Default settings at Power-up.
AIN 4 REGISTER MSBS (Read) [Add. = 0Bh]
D7 T9 0*
D6 T8 0*
D5 T7 0*
D4 T6 0*
D3 T5 0*
D2 T4 0*
D1 T3 0*
D0 T2 0*
This 8-bit read register contains the 8 MSBs of the AIN 4 analog input voltage word. The value in this register is combined with bits D6:7 of the External Temperature Value and Analog Inputs 1-4 Register LSBs, address 04h, to give the full 10-bit conversion result of the analog value on the AIN 4 pin.
Table 16. AIN 4 MSBs
*Default settings at Power-up.
EXTERNAL TEMPERATURE VALUE OR ANALOG INPUT AIN 1 REGISTER MSBS (Read only) [Add. = 08h]
D7 MSB 0*
D6 A8 0*
D5 A7 0*
D4 A6 0*
D3 A5 0*
D2 A4 0*
D1 A3 0*
D0 A2 0*
This 8-bit read only register stores, if selected, the External Temperature value or the Analog Input AIN 1 value. Selection is done in Control Configuration 1 register. The external temperature value is stored in twos complement format. The 8 MSBs of the 10-bit value are stored in this register.
Table 13. External Temperature Value/Analog Inputs MSBs
*Default settings at Power-up.
DAC A REGISTER LSBS (Read/Write) [Add. = 10h]
This 8-bit read/write register contains the 4/2 LSBs of the ADT7516/7517 DAC A word respectivily. The value in this register is combined with the value in the DAC A Register MSBs and converted to an analog voltage on the VOUTA pin. On power-up the voltage output on the VOUTA pin is 0 V.
Table 17. DAC A (ADT7516) LSBs
D7
D6
D5
D4
D3 T/A5 0*
D2
D1
D0 T/A2 0* D7 B3 0* D6 B2 0* D5 B1 0* D4 LSB 0* D3 N/A N/A D2 N/A N/A D1 N/A N/A D0 N/A N/A
T/A9 T/A8 T/A7 T/A6 0* 0* 0* 0*
T/A4 T/A3 0* 0*
*Default settings at Power-up.
AIN 2 REGISTER MSBS (Read) [Add. = 09h]
This 8-bit read register contains the 8 MSBs of the AIN 2 analog input voltage word. The value in this register is combined with bits D2:3 of the External Temperature Value and Analog Inputs 1-4 Register LSBs, address 04h, to give the full 10-bit conversion result of the analog value on the AIN 2 pin.
Table 14. AIN 2 MSBs
*Default settings at Power-up.
Table 18. DAC A (ADT7517) LSBs
D7 B1 0*
D6 LSB 0*
D5 N/A N/A
D4 N/A N/A
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
*Default settings at Power-up.
D7 MSB 0*
D6 A8 0*
D5 A7 0*
D4 A6 0*
D3 A5 0*
D2 A4 0*
D1 A3 0*
D0 A2 0*
DAC A REGISTER MSBS (Read/Write) [Add. = 11h]
*Default settings at Power-up.
AIN 3 REGISTER MSBS (Read) [Add. = 0Ah]
This 8-bit read/write register contains the 8 MSBs of the DAC A word. The value in this register is combined with the value in the DAC A Register LSBs and converted to an analog voltage on the VOUTA pin. On power-up the voltage output on the VOUTA pin is 0 V.
Table 19. DAC A MSBs
This 8-bit read register contains the 8 MSBs of the AIN 3 analog input voltage word. The value in this register is combined with bits D4:5 of the External Temperature Value and Analog Inputs 1-4 Register LSBs, address 04h,
D7
D6
D5
D4
D3
D2
D1
D0
-26-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
MSB 0* B8 0* B7 0* B6 0* B5 0* B4 0* B3 0* B2 0* D7 B1 0* D6 LSB 0* D5 N/A N/A D4 N/A N/A D3 N/A N/A D2 N/A N/A D1 N/A N/A D0 N/A N/A
*Default settings at Power-up.
*Default settings at Power-up.
DAC B REGISTER LSBS (Read/Write) [Add. = 12h]
This 8-bit read/write register contains the 4/2 LSBs of the ADT7516/7517 DAC B word respectivily. The value in this register is combined with the value in the DAC B Register MSBs and converted to an analog voltage on the VOUTB pin. On power-up the voltage output on the VOUTB pin is 0 V.
Table 20. DAC B (ADT7516) LSBs
DAC C REGISTER MSBS (Read/Write) [Add. = 15h]
This 8-bit read/write register contains the 8 MSBs of the DAC C word. The value in this register is combined with the value in the DAC C Register LSBs and converted to an analog voltage on the VOUTC pin. On power-up the voltage output on the VOUTC pin is 0 V.
Table 25. DAC C MSBs
D7 B3 0*
D6 B2 0*
D5 B1 0*
D4 LSB 0*
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
D7 MSB 0*
D6 B8 0*
D5 B7 0*
D4 B6 0*
D3 B5 0*
D2 B4 0*
D1 B3 0*
D0 B2 0*
*Default settings at Power-up.
*Default settings at Power-up.
Table 21. DAC B (ADT7517) LSBs
DAC D REGISTER LSBS (Read/Write) [Add. = 16h]
D7 B1 0*
D6 LSB 0*
D5 N/A N/A
D4 N/A N/A
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
*Default settings at Power-up.
This 8-bit read/write register contains the 4/2 LSBs of the ADT7516/7517 DAC D word respectivily. The value in this register is combined with the value in the DAC D Register MSBs and converted to an analog voltage on the VOUTD pin. On power-up the voltage output on the VOUTD pin is 0 V.
Table 26. DAC D (ADT7516) LSBs
DAC B REGISTER MSBS (Read/Write) [Add. = 13h]
This 8-bit read/write register contains the 8 MSBs of the DAC B word. The value in this register is combined with the value in the DAC B Register LSBs and converted to an analog voltage on the VOUTB pin. On power-up the voltage output on the VOUTB pin is 0 V.
Table 22. DAC B MSBs
D7 B3 0*
D6 B2 0*
D5 B1 0*
D4 LSB 0*
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
*Default settings at Power-up.
Table 27. DAC D (ADT7517) LSBs
D7 MSB 0*
D6 B8 0*
D5 B7 0*
D4 B6 0*
D3 B5 0*
D2 B4 0*
D1 B3 0*
D0 B2 0* D7 B1 0* D6 LSB 0* D5 N/A N/A D4 N/A N/A D3 N/A N/A D2 N/A N/A D1 N/A N/A D0 N/A N/A
*Default settings at Power-up.
*Default settings at Power-up.
DAC C REGISTER LSBS (Read/Write) [Add. = 14h]
This 8-bit read/write register contains the 4/2 LSBs of the ADT7516/7517 DAC C word respectivily. The value in this register is combined with the value in the DAC C Register MSBs and converted to an analog voltage on the VOUTC pin. On power-up the voltage output on the VOUTC pin is 0 V.
Table 23. DAC C (ADT7516) LSBs
DAC D REGISTER MSBS (Read/Write) [Add. = 17h]
This 8-bit read/write register contains the 8 MSBs of the DAC D word. The value in this register is combined with the value in the DAC D Register LSBs and converted to an analog voltage on the VOUTD pin. On power-up the voltage output on the VOUTD pin is 0 V.
Table 28. DAC D MSBs
D7 B3 0*
D6 B2 0*
D5 B1 0*
D4 LSB 0*
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
D7 MSB 0*
D6 B8 0*
D5 B7 0*
D4 B6 0*
D3 B5 0*
D2 B4 0*
D1 B3 0*
D0 B2 0*
*Default settings at Power-up.
*Default settings at Power-up.
Table 24. DAC C (ADT7517) LSBs
REV. PrH
-27-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
CONTROL CONFIGURATION 1 REGISTER (Read/ Write) [Add. = 18h]
C7 0*
C6 0*
C5 0*
C4 0*
C3 0*
C2 0*
C1 0*
C0 0*
This configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7516/17/18.
Table 29. Control Configuration 1
*Default settings at Power-up.
Bit C2:0 D0 C0 0* D7 PD 0* D6 C6 0* D5 C5 0* D4 C4 0* D3 C3 0* D2 C2 0* D1 C1 0*
Function In single channel mode these bits select between VDD, the internal temperature sensor, external temperature sensor/AIN1, AIN2, AIN3 and AIN4 for conversion. Default is VDD. 000 = VDD 001 = Internal Temperature Sensor. 010 = External Temperature Sensor/AIN1 (Bits C1:C2 of Control Configuration 1 affect this selection) 011 = AIN2 100 = AIN3 101 = AIN4 110 - 111 = RESERVED RESERVED Selects between single channel and Round Robin conversion cycle. Default is Round Robin. 0 = Round Robin. 1 = Single Channel. Default condition is to average every measurement on all channels 16 times. This bit disables this averaging. Channels affected are temperature, analog inputs and VDD. 0 = Enable averaging. 1 = Disable averaging. SMBus timeout on the serial clock puts a 25ms limit on the pulse width of the clock. Ensures that a fault on the master SCL does not lock up the SDA line. 0 = Disable SMBus Timeout. 1 = Enable SMBus Timeout. Software Reset. Setting this bit to a 1 causes a software reset. All registers and DAC outputs will reset to their default settings.
*Default settings at Power-up.
Bit C0
Function This bit enables/disables conversions in Round Robin and Single Channel mode. ADT7516/17/ 18 powers up in Round Robin mode but monitoring is not initiated until this bit is set. Default = 0. 0 = Stop monitoring. 1 = Start monitoring. Selects between the two different analog inputs on pins 7 and 8. ADT7516/17/18 powers up with AIN1 and AIN2 selected. 00 AIN1 and AIN2 selected. 01 Undefined. 10 External TDM selected. 11 Undefined. Selects between digital (LDAC) and analog inputs (AIN3) on pin 9. When AIN3 is selected, Bit C3 of Control Configuration 3 register is masked out and has no affect until LDAC is selected as the input on pin 9. 0 LDAC selected. 1 AIN3 selected. RESERVED. Write 0 only. 0 1 Enable INT/INT Output Disable INT/INT Output
C3 C4
C2:C1
C5
C3
C6
C4 C5 C6
C7
Configures INT/INT output polarity. 0 = Active low 1 = Active High Power-down Bit. Setting this bit to 1 puts the ADT7516/17/18 into standby mode. In this mode both ADC and DACs are fully powered down, but serial interface is still operational. To power up the part again just write 0 to this bit.
CONTROL CONFIGURATION 3 REGISTER (Read/ Write) [Add. = 1Ah]
PD
This configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7516/17/18.
Table 31. Control Configuration 3
D7
CONTROL CONFIGURATION 2 REGISTER (Read/ Write) [Add. = 19h]
D6 C6 0*
D5 C5 0*
D4 C4 0*
D3 C3 0*
D2 C2 0*
D1 C1 0*
D0 C0 0*
C7 0*
This configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7516/17/18.
Table 30. Control Configuration 2
*Default settings at Power-up.
Bit D0 C0
Function Selects between fast and normal ADC conversion speeds. REV. PrH
D7
D6
D5
D4
D3
D2
D1
-28-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
0 = ADC clock at 1.4 KHz. 1 = ADC clock at 22.5 KHz. Analog filters are disabled. C1 On the ADT7516 and ADT7517, this bit selects between 8 bits and 10 bits DAC output resolution on the Thermal Voltage Output feature. Default = 8 bits. This bit has no affect on the ADT7518 output as this part has only an 8-bit DAC. In the ADT7518 case, write 0 to this bit. 0 = 8 bits resolution. 1 = 10 bits resolution. RESERVED. Only write 0. 0 = LDAC pin controls updating of DAC outputs. 1 = DAC Configration register and LDAC Configuration register control updating of DAC outputs. Selects the ADC reference to be either Internal VREF or VDD for analog inputs. 0 = Int VREF 1 = VDD Setting this bit selects DAC A voltage output to be proportional to the internal temperature measurement. Setting this bit selects DAC B voltage output to be proportional to the external temperature measurement. RESERVED. Write 0 only. D3 Selects the output range of DAC D. 0 = 0 V to VREF. 1 = 0 V to 2VREF. 00 MSB write to any DAC register generates LDAC command which updates that DAC only. MSB write to DAC B or DAC D register generates LDAC command which updates DACs A, B or DACs C, D respectivily. MSB write to DAC D register generates LDAC command which updates all 4 DACs. LDAC command generated from LDAC register.
D5:D4
01
10
C2 C3
11 D6:D7
RESERVED. Write 0's only.
C4
LDAC CONFIGURATION REGISTER (Write only) [Add. = 1Ch]
C5
This configuration register is an 8-bit write register that is used to control the updating of the quad DAC outputs if the LDAC pin is disabled and Bits D4 and D5 of DAC Configuration register are both set to 1. Also selects either the internal or external VREF for all four DACs. Bits D0D3 in this register are self clearing i.e. reading back from this register will always give 0's for these bits.
Table 33. LDAC Configuration
C6
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
C7
DAC CONFIGURATION REGISTER (Read/Write) [Add. = 1Bh]
*Default settings at Power-up.
This configuration register is an 8-bit read/write register that is used to control the output ranges of all four DACs and also to control the loading of the DAC registers if the LDAC pin is disabled (bit C3 = 1, Control Configuration 3 register).
Table 32. DAC Configuration
Bit D0 D1
Function Writing a 1 to this bit will generate the LDAC command to update DAC A output only. Writing a 1 to this bit will generate the LDAC command to update DAC B output only. Writing a 1 to this bit will generate the LDAC command to update DAC C output only. Writing a 1 to this bit will generate the LDAC command to update DAC D output only. Selects either internal VREF or external VREF for DACs A and B. 0 = External VREF 1 = Internal VREF Selects either internal VREF or external VREF for DACs C and D. 0 = External VREF 1 = Internal VREF RESERVED. Only write 0's.
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
D2 D3 D4
*Default settings at Power-up.
Bit D0
Function Selects the output range of DAC A. 0 = 0 V to VREF. 1 = 0 V to 2VREF. Selects the output range of DAC B. 0 = 0 V to VREF. 1 = 0 V to 2VREF. Selects the output range of DAC C. 0 = 0 V to VREF. 1 = 0 V to 2VREF. -29- D5
D1
D6:D7
D2
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
INTERRUPT MASK 1 REGISTER (Read/Write) [Add. = 1Dh] INTERNAL TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 1Fh]
This mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the INT/ INT pin to go active.
Table 34. Interrupt Mask 1
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
*Default settings at Power-up.
This register contains the Offset Value for the Internal Temperature Channel. A 2's complement number can be written to this register which is then 'added' to the measured result before it is stored or compared to limits. In this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. As it is an 8-bit register the temperature resolution is 1oC.
Table 36. Internal Temperature Offset
Bit D0 D1 D2
Function 0 = Enable internal THIGH interrupt. 1 = Disable internal THIGH interrupt. 0 = Enable internal TLOW interrupt. 1 = Disable internal TLOW interrupt. 0 = Enable external THIGH interrupt or AIN1 interrupt. 1 = Disable external THIGH interrupt or AIN1 interrupt. 0 = Enable external Tlow interrupt. 1 = Disable external Tlow interrupt. 0 = Enable external temperature fault interrupt. 1 = Disable external temperature fault interrupt. 0 = Enable AIN2 interrupt. 1 = Disable AIN2 interrupt. 0 = Enable AIN3 interrupt. 1 = Disable AIN3 interrupt. 0 = Enable AIN4 interrupt. 1 = Disable AIN4 interrupt. D7 D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
*Default settings at Power-up.
EXTERNAL TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 20h]
D3 D4 D5 D6 D7
This register contains the Offset Value for the Internal Temperature Channel. A 2's complement number can be written to this register which is then 'added' to the measured result before it is stored or compared to limits. In this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. As it is an 8-bit register the temperature resolution is 1oC.
Table 37. External Temperature Offset
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
INTERRUPT MASK 2 REGISTER (Read/Write) [Add. = 1Eh]
D7 0*
This mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the INT/ INT pin to go active.
Table 35. Interrupt Mask 2
*Default settings at Power-up.
INTERNAL ANALOG TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 21h]
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
*Default settings at Power-up.
Bit D0:D3 D4 D5:D7
Function RESERVED. Only write 0's. 0 = Enable VDD interrupts. 1 = Disable VDD interrupts. RESERVED. Only write 0's.
This register contains the Offset Value for the Internal Thermal Voltage output. A 2's complement number can be written to this register which is then 'added' to the measured result before it is converted by DAC A. Varying the value in this register has the affect of varying the temperature span. For example, the output voltage can represent a temperature span of -128oC to +127oC or even 0oC to +127oC. In essence this register changes the position of 0V on the temperature scale. Anything other than -128oC to +127oC will produce an upper deadband on the DAC A output. As it is an 8-bit register the temperature resolution is 1oC. Default value is -40oC.
Table 38. Internal Analog Temperature Offset
D7 -30-
D6
D5
D4
D3
D2
D1
D0 REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
D7 1* D6 1* D5 0* D4 1* D3 1* D2 0* D1 0* D0 0*
*Default settings at Power-up.
upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured Internal Temperature Value has to be greater than the value in this register. As it is an 8-bit register the temperature resolution is 1oC. Default value is +100oC.
Table 42. Internal THIGH Limit
EXTERNAL ANALOG TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 22h]
This register contains the Offset Value for the External Thermal Voltage output. A 2's complement number can be written to this register which is then 'added' to the measured result before it is converted by DAC B. Varying the value in this register has the affect of varying the temperature span. For example, the output voltage can represent a temperature span of -128oC to +127oC or even 0oC to +127oC. In essence this register changes the position of 0V on the temperature scale. Anything other than -128oC to +127oC will produce an upper deadband on the DAC B output. As it is an 8-bit register the temperature resolution is 1oC. Default value is -40oC.
Table 39. External Analog Temperature Offset
D7 D7 0*
D6 D6 1*
D5 D5 1*
D4 D4 0*
D3 D3 0*
D2 D2 1*
D1 D1 0*
D0 D0 0*
*Default settings at Power-up.
INTERNAL TLOW LIMIT REGISTER (Read/Write) [Add. = 26h]
D7 D7 1*
D6 D6 1*
D5 D5 0*
D4 D4 1*
D3 D3 1*
D2 D2 0*
D1 D1 0*
D0 D0 0*
This limit register is an 8-bit read/write register which stores the 2's complement of the internal temperature lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured Internal Temperature Value has to be more negative than or equal to the value in this register. As it is an 8-bit register the temperature resolution is 1oC. Default value is -55oC.
Table 43. Internal TLOW Limit
*Default settings at Power-up.
D7
VDD VHIGH LIMIT REGISTER (Read/Write) [Add. = 23h]
D6 D6 1*
D5 D5 0*
D4 D4 0*
D3 D3 1*
D2 D2 0*
D1 D1 0*
D0 D0 1*
This limit register is an 8-bit read/write register which stores the VDD upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured VDD value has to be greater than the value in this register. Default value is 5.46 V.
Table 40. VDD VHIGH Limit
D7 1*
*Default settings at Power-up.
EXTERNAL THIGH / AIN1 VHIGH LIMIT REGISTER (Read/Write) [Add. = 27h]
D7 D7 1*
D6 D6 1*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 1*
D1 D1 1*
D0 D0 1*
*Default settings at Power-up.
VDD VLOW LIMIT REGISTER (Read/Write) [Add. = 24h]
If pins 7 and 8 are configured for the external temperature sensor then this limit register is an 8-bit read/write register which stores the 2's complement of the external temperature upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured External Temperature Value has to be greater than the value in this register. As it is an 8-bit register the temperature resolution is 1oC. Default value = -1 o C. If pins 7 and 8 are configured for AIN1 and AIN2 inputs then this limit register is an 8-bit read/write register which stores the AIN1 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured AIN1 value has to be greater than the value in this register. As it is an 8-bit register the resolution is four times less than the resolution of the 10Bit ADC. As the power-up default settings for pins 7 and 8 is AIN1 and AIN2 inputs then the default value for this limit register is fullscale voltage.
Table 44. AIN1 VHIGH Limit
This limit register is an 8-bit read/write register which stores the VDD lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured VDD value has to be less than or equal to the value in this register. Default value is 2.7 V.
Table 41. VDD VHIGH Limit
D7 D7 0*
D6 D6 1*
D5 D5 1*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 1*
D0 D0 0*
*Default settings at Power-up.
INTERNAL THIGH LIMIT REGISTER (Read/Write) [Add. = 25h]
D7 D7 1* -31-
D6 D6 1*
D5 D5 1*
D4 D4 1*
D3 D3 1*
D2 D2 1*
D1 D1 1*
D0 D0 1*
This limit register is an 8-bit read/write register which stores the 2's complement of the internal temperature REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
*Default settings at Power-up.
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
EXTERNAL TLOW / AIN1 VLOW LIMIT REGISTER (Read/Write) [Add. = 28h]
If pins 7 and 8 are configured for the external temperature sensor then this limit register is an 8-bit read/write register which stores the 2's complement of the external temperature lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured External Temperature Value has to be more negative than or equal to the value in this register. As it is an 8-bit register the temperature resolution is 1oC. Default value = 0oC.
*Default settings at Power-up.
AIN3 VHIGH LIMIT REGISTER (Read/Write) [Add. = 2Dh]
If pins 7 and 8 are configured for AIN1 and AIN2 inputs then this limit register is an 8-bit read/write register which stores the AIN1 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured AIN1 value has to be less than or equal to the value in this register. As it is an 8-bit register the resolution is four times less than the resolution of the 10-Bit ADC. As the power-up default settings for pins 7 and 8 is AIN1 and AIN2 inputs then the default value for this limit register is 0 V.
Table 45. AIN1 VLOW Limit
This limit register is an 8-bit read/write register which stores the AIN3 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured AIN3 value has to be greater than the value in this register. As it is an 8-bit register the resolution is four times less than the resolution of the 10Bit ADC. Default value is fullscale voltage.
Table 48. AIN3 VHIGH Limit
D7 D7 1*
D6 D6 1*
D5 D5 1*
D4 D4 1*
D3 D3 1*
D2 D2 1*
D1 D1 1*
D0 D0 1*
*Default settings at Power-up.
AIN3 VLOW LIMIT REGISTER (Read/Write) [Add. = 2Eh]
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
*Default settings at Power-up.
This limit register is an 8-bit read/write register which stores the AIN3 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured AIN3 value has to be less than or equal to the value in this register. As it is an 8-bit register the resolution is four times less than the resolution of the 10-Bit ADC. Default value is 0 V.
Table 49. AIN3 VLOW Limit
AIN2 VHIGH LIMIT REGISTER (Read/Write) [Add. = 2Bh]
This limit register is an 8-bit read/write register which stores the AIN2 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured AIN2 value has to be greater than the value in this register. As it is an 8-bit register the resolution is four times less than the resolution of the 10Bit ADC. Default value is fullscale voltage.
Table 46. AIN2 VHIGH Limit
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
*Default settings at Power-up.
AIN4 VHIGH LIMIT REGISTER (Read/Write) [Add. = 2Fh]
D7 D7 1*
D6 D6 1*
D5 D5 1*
D4 D4 1*
D3 D3 1*
D2 D2 1*
D1 D1 1*
D0 D0 1*
*Default settings at Power-up.
This limit register is an 8-bit read/write register which stores the AIN4 input upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured AIN4 value has to be greater than the value in this register. As it is an 8-bit register the resolution is four times less than the resolution of the 10Bit ADC. Default value is fullscale voltage.
Table 50. AIN4 VHIGH Limit
AIN2 VLOW LIMIT REGISTER (Read/Write) [Add. = 2Ch]
This limit register is an 8-bit read/write register which stores the AIN2 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured AIN2 value has to be less than or equal to the value in this register. As it is an 8-bit register the resolution is four times less than the resolution of the 10-Bit ADC. Default value is 0 V.
Table 47. AIN2 VLOW Limit
D7 D7 1*
D6 D6 1*
D5 D5 1*
D4 D4 1*
D3 D3 1*
D2 D2 1*
D1 D1 1*
D0 D0 1*
*Default settings at Power-up.
-32-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
AIN4 VLOW LIMIT REGISTER (Read/Write) [Add. = 30h]
This limit register is an 8-bit read/write register which stores the AIN4 input lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen the measured AIN4 value has to be less than or equal to the value in this register. As it is an 8-bit register the resolution is four times less than the resolution of the 10-Bit ADC. Default value is 0 V.
Table 51. AIN4 VLOW Limit
Stepping contains the manufacturers code for minor revisions or steppings to the silicon. The Version is the ADT7516/17/18 version number. The ADT7516/17/18's version number is 0100b (4h).
SPI LOCK STATUS REGISTER (Read only) [Add. = 7Fh]
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
Bit the will 0 1
D0 (LSB) of this read only register indicates whether SPI interface is locked or not. Writing to this register cause the device to malfunction. Default value is 00h. = I2C interface = SPI interface selected and locked.
ADT7516/7517/7518 SERIAL INTERFACE
*Default settings at Power-up.
DEVICE ID REGISTER (Read only) [Add. = 4Dh]
This 8-bit read only register indicates which part the device is in the model range. ADT7516 = 03h, ADT7517 = 07h and ADT7518 = 0Bh.
MANUFACTURER'S ID REGISTER (Read only) [Add. = 4Eh]
There are two serial interfaces that can be used on this part, I2C and SPI. The device will power up with the serial interface in I2C mode but it is not locked into this mode. To stay in I2C mode it is recommended that the user ties the CS line to either VCC or GND. It is not possible to lock the I2C mode but it is possible to select and lock the SPI mode. To select and lock the interface into the SPI mode, a number of pulses must be sent down the CS (pin 4) line. The following section describes how this is done. Once the SPI communication protocol has been locked in, it cannot be unlocked while the device is still powered up. Bit D0 of SPI Lock Status register (address = 7Fh) is set to 1 when a successful SPI interface lock has been acomplished. To reset the serial interface the user must
This register contains the manufacturers identification number. ADI's is 41h.
SILICON REVISION REGISTER (Read only) [Add. = 4Fh]
This register is divided into the four lsbs representing the Stepping and the four msbs representing the Version. The
CS (Start High)
A
B
C
SPI LOCKED ON 3RD RISING EDGE
SPI FRAMING EDGE
Figure 22(a). Serial Interface - Selecting and Locking SPI Protocol
CS (Start Low)
A
B
C
SPI LOCKED ON 3RD RISING EDGE
SPI FRAMING EDGE
Figure 22(b). Serial Interface - Selecting and Locking SPI Protocol
REV. PrH
-33-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
power down the part and power up again. A software reset does not reset the serial interface.
SERIAL INTERFACE SELECTION
ADT7516/17/18
CS SDA SCL I2C ADDRESS = 1001 000 ADD VDD VDD
The CS line controls the selection between I2C and SPI. Figure 22 shows the selection process necessary to lock the SPI interface mode. If the user wants to communicate to the ADT7516/17/18 using the SPI protocol, send three pulses down the CS line as shown in figure 22(a) and 22(b). On the third rising edge (marked as C in figure 22) the part selects and locks the SPI interface. The user is now limited to communicating to the device using the SPI protocol. As per most SPI standards, the CS line must be low during every SPI communication to the ADT7516/17/18 and high all other times. Typical examples of how to connect up the dual interface as I2C or SPI is shown in figures 23(a) and 23(b).
Figure 23(a). Typical I2C Interface Connection
ADT7516/17/18
CS DIN SCLK DOUT
LOCK AND SELECT SPI
SPI FRAMING EDGE
Figure 23(b). Typical SPI Interface Connection
1
9
1
9
SCL
SDA START BY MASTER
1
0
0
1
A2
A1
A0
R/W
ACK. BY ADT7516/17/18
P7
P6
P5
P4
P3
P2
P1
P0 ACK. BY ADT7516/17/18 STOP BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 ADDRESS POINTER REGISTER BYTE
Figure 24. I2C - Writing to the Address Pointer Register to select a register for a subsequent Read operation
1
9
1
9
SCL
SD A START BY MASTER
1
0
0
1
A2
A1
A0
R/W
ACK. BY ADT7516/17/18
P7
P6
P5
P4
P3
P2
P1
P0 ACK. BY ADT7516/17/18
FRAME 1 SERIAL BUS ADDRESS BYTE
1
SCL (CONTINUED)
FRAME 2 ADDRESS POINTER REGISTER BYTE
9
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7516/17/18 STOP BY MASTER
FRAME 3 DATA BYTE
Figure 25. I2C - Writing to the Address Pointer Register followed by a single byte of data to the selected register
-34-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
The following sections describe in detail how to use the I2 C and SPI protocols associated with the ADT7516/17/ 18.
I2C SERIAL INTERFACE
Consult SMBus specification (www.smbus.org) for more information. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SDA whilst the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits, consisting of a 7-bit address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit. All other devices on the bus now remain idle whilst the selected device waits for data to be read from or written to it. If the R/W bit is a 0 then the master will write to the slave device. If the R/W bit is a 1 the master will read from the slave device.
Like all I2 C-compatible devices, the ADT7516/7517/7518 has an 7-bit serial address. The four MSBs of this address for the ADT7516/7517/7518 are set to 1001. The three LSBs are set by pin 11, ADD. The ADD pin can be configured three ways to give three different address options; low, floating and high. Setting the ADD pin low gives a serial bus address of 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011. There is an enable/disable bit for the SMBus timout. When this is enabled the SMBus will timeout after 25 ms of no activity. To enable it, set Bit 6 of Control Configuration 2 register. The power-on default is with the SMBus timeout disabled. The ADT7516/17/18 supports SMBus Packet Error Checking (PEC) and it's use is optional. It is triggered by supplying the extra clocks for the PEC byte. The PEC is calculated using CRC-8. The Frame Clock Sequence (FCS) conforms to CRC-8 by the polynominal :
C(x) = x8 + x2 + x1 + 1
1
SCL
9
1
9
SDA START BY MASTER
1
0
0
1
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY ADT7516/17/18 FRAME 1 SERIAL BUS ADDRESS BYTE
NO ACK. BY MASTER
FRAME 2 SINGL E DATA BYTE FROM ADT7516/17/18
STOP BY MASTER
Figure 26. I2C - Reading a single byte of data from a selected register
CS 1 SCLK 8 1 8
DIN
D7 START
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
WRITE COMMAND
REGISTER ADDRESS
CS (CONTINUED) 1 SCLK (CONTINUED) 8
DIN (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 STOP
DATA BYTE
Figure 27. SPI - Writing to the Address Pointer Register followed by a single byte of data to the selected register
REV. PrH
-35-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
2. Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge Bit from the receiver of data. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal. 3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will pull the data line high during the low period before the 9th clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. The I C address set up by the ADD pin is not latched by the device until after this address has been sent twice. On the 8th SCL cycle of the second valid communication, the serial bus address is latched in. This is the SCL cycle
2
directly after the device has seen it's own I2C serial bus address. Any subsequent changes on this pin will have no affect on the I2C serial bus address.
WRITING TO THE ADT7516/7517/7518
Depending on the register being written to, there are two different writes for the ADT7516/7517/7518. It is not possible to do a block write to this part i.e no I2C autoincrement.
Writing to the Address Pointer Register for a subsequent read.
In order to read data from a particular register, the Address Pointer Register must contain the address of that register. If it does not, the correct address must be written to the Address Pointer Register by performing a singlebyte write operation, as shown in Figure 24. The write operation consists of the serial bus address followed by the address pointer byte. No data is written to any of the data registers. A read operation is then performed to read the register.
Writing data to a Register.
All registers are 8-bit registers so only one byte of data can be written to each register. Writing a single byte of data to one of these Read/Write registers consists of the serial bus address, the data register address written to the Address Pointer Register, followed by the data byte written
CS 1 SCLK 8 1 8
DIN
D7 START
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0 STOP
WRITE COMMAND
REGISTER ADDRESS
Figure 28. SPI - Writing to the Address Pointer Register to select a register for a subsequent read operation
CS 1 SCLK 8 1 8
DIN
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DOUT
X START
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0 STOP
READ COMMAND
DATA BYTE 1
Figure 29. SPI - Reading a single byte of data from a selected register
-36-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
to the selected data register. This is illustrated in Figure 25. To write to a different register, another START or repeated START is required. If more than one byte of data is sent in one communication operation, the addressed register will be repeately loaded until the last data byte has been sent.
READING DATA FROM THE ADT7516/7517/7518 SPI SERIAL INTERFACE
Reading data from the ADT7516/7517/7518 is done in a one byte operation. Reading back the contents of a register is shown in Figure 26. The register address previously having been set up by a single byte write operation to the Address Pointer Register. If you want to read from another register then you will have to write to the Address Pointer Register again to set up the relevant register address. Thus block reads are not possible i.e. no I2C auto-increment.
The SPI serial interface of the ADT7516/7517/7518 consists of four wires, CS, SCLK, DIN and DOUT. The CS is used to select the device when more than one device is connected to the serial clock and data lines. The CS is also used to distinguish between any two seperate serial communications, reference Figure 31 for graphical explanation. The SCLK is used to clock data in and out of the part. The DIN line is used to write to the registers and the DOUT line is used to read data back from the registers. The part operates in a slave mode and requires an externally applied serial clock to the SCLK input. The serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. There are two types of serial operations, a read and a write. Command words are used to distinguish between a read and a write operation. These command words are
CS 1 SCLK 8 1 8
DIN
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DOUT
X START
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
READ COMMAND
DATA BYTE 1
CS (CONTINUED)
1 SCLK (CONTINUED)
8
DIN (CONTINUED) DOUT (CONTINUED)
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0 STOP
DATA BYTE 2
Figure 30. SPI - Reading a two bytes of data from two sequential registers
CS
SPI
READ OPERATION
WRITE OPERATION
Figure 31. SPI - Correct use of CS during SPI communication
REV. PrH
-37-
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
given in Table 52. Address auto-increment is possible in SPI mode.
Table 52. SPI COMMAND WORDS
WRITE 90h (1001 0000)
Write Operation
READ 91h (1001 0001)
The INT/INT output becomes active when either the Internal Temperature Value, the External Temperature Value, VDD Value or any of the AIN input values exceed the values in their corresponding THIGH/VHIGH or TLOW/ VLOW Registers. The INT/INT output goes inactive again when a conversion result has the measured value back within the trip limits. The two Interrupt Status registers show which event caused the INT/INT pin to go active. The INT/INT output requires an external pull-up resistor. This can be connected to a voltage different from VDD provided the maximum voltage rating of the INT/INT output pin is not exceeded. The value of the pull-up resistor depends on the application, but should be as large enough to avoid excessive sink currents at the INT/INT output, which can heat the chip and affect the temperature reading.
Figure 27 shows the timing diagram for a write operation to the ADT7516/7517/7518. Data is clocked into the registers on the rising edge of SCLK. When the CS line is high the DIN and DOUT lines are in three-state mode. Only when the CS goes from a high to a low does the part accept any data on the DIN line. In SPI mode the Address Pointer Register is capable of auto-incrementing to the next register in the register map without having to load the Address Pointer register each time. In Figure 27 the register address portion of the diagram gives the first register that will be written to. Subsequent data bytes will be written into sequential writable registers. Thus after each data byte has been written into a register, the Address Pointer Register auto increments it's value to the next available register. The Address Pointer Register will autoincrement from 00h to 3Fh and will loop back to start all over again at 00h when it reaches 3Fh.
Read Operation
Figures 28 to 30 show the timing diagrams necessary to accomplish correct read operations. To read back from a register you first have to write to the Address Pointer Register with the address of the register you wish to read from. This operation is shown in Figure 28. Figure 29 shows the procedure for reading back a single byte of data. The read command is first sent to the part during the first 8 clock cycles, during the following 8 clock cycles the data contained in the register selected by the Address Pointer register is outputted onto the DOUT line. Data is outputted onto the DOUT line on the falling edge of SCLK. Figure 30 shows the procedure when reading data from two sequential registers. Multiple data reads are possible in SPI interface mode as the Address Pointer Register is auto-incremental. The Address Pointer Register will auto-increment from 00h to 3Fh and will loop back to start all over again at 00h when it reaches 3Fh.
SMBUS/SPI INT/INT
The ADT7516/17/18 INT/INT output is an interrupt line for devices that want to trade their ability to master for an extra pin. The ADT7516/17/18 is a slave only device and uses the SMBus/SPI INT/INT to signal the host device that it wants to talk. The SMBus/SPI INT/INT on the ADT7516/17/18 is used as an over/under limit indicator. The INT/INT pin has an open-drain configuration which allows the outputs of several devices to be wired-AND together when the INT/INT pin is active low. Use C6 of the Control Configuration 1 Register to set the active polarity of the INT/INT output. The power-up default is active low. The INT/INT output can be disabled or enabled by setting C5 of Control Configuration 1 Register to a 1 or 0 respectively.
-38-
REV. PrH
PRELIMINARY TECHNICAL DATA ADT7516/7517/7518
Outline Dimensions (Dimensions shown in inches and mm ) 16-Lead QSOP Package ( RQ-16 )
0.19 7 (5.00) 0.18 9 (4.80)
16
9
0.157 (3.99) 0.150 (3.81)
1 8
0.24 4 (6.20) 0.22 8 (5.79)
P IN 1 0 .059 (1.50 ) MAX 0.069 (1.75) 0.053 (1.35)
0.010 (0.25) 0.004 (0.10)
0.025 (0.64) BSC
0.012 (0.30 ) 0.008 (0.20 )
SEATING PLANE
0.010 (0.20) 0.007 (0.18)
8o o 0
REV. PrH
-39-
This datasheet has been download from: www..com Datasheets for electronics components.

▲Up To Search▲

Price & Availability of ADT7518ARQ

	To Download ADT7518ARQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .